ADSP-BF523C(RevPrC) 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

ADSP-BF523C
(Rev.:RevPrC)

Blackfin® Embedded Processor

Analog Devices 

Preliminary Technical Data

ADSP-BF523C/ADSP-BF525C/ADSP-BF527C

there is more than one master clock available, it is recom-

mended that the clock be generated by the CODEC to maximize

performance.

CODEC_CLKOUT

The CODEC clock is available to the external audio system on

the CODEC_CLKOUT pin. The CODEC clock is buffered for

driving external loads. There is no phase inversion between

XTI/CODEC_MCLK, the CODEC clock and

CODEC_CLKOUT but there will inevitably be some delay. The

delay will be dependent on the load that CODEC_CLKOUT

drives. See Electrical Characteristics on Page 32.

CODEC_CLKOUT can also be divided by two. See Table 13 for

the software control.

CODEC_CLKOUT is disabled and set low whenever the device

is in reset.

Table 13. Programming CODEC_CLKOUT

Register Bit Label

Address

Default Description

000 1000 7 CLKODIV2 0

CODEC Clock Divider Select

1 = CODEC_CLKOUT is

CODEC Clock ÷ 2

0 = CODEC_CLKOUT is

CODEC Clock

If CODEC_CLKOUT is not needed, the CODEC_CLKOUT

buffer on the CODEC can be safely powered down to conserve

power (see Power Down Modes on Page 25). If the programmer

has a choice, fCODEC_CLKOUT = f CODEC_MCLK /2 is recommended to

conserve power. CODEC_CLKOUT changes on the rising edge

of CODEC_MCLK when f CODEC_MCLK /2 is selected.

DIGITAL AUDIO INTERFACES

The CODEC accommodates four digital audio interface

formats.

• Right justified

• Left justified

• I2S

• Frame Sync mode

These are shown in Figure 19 on Page 17 to Figure 23 on

Page 19. See Electrical Characteristics on Page 32 for timing

information. These modes operate with 16-bit to 32-bit data

except that 32-bit data is not supported in right justified mode.

All four of these modes are MSB first.

The digital audio interface takes the data from the internal ADC

digital filter and places it on the ADCDAT output. ADCDAT is

the formatted digital audio data stream output from the ADC

digital filters with left and right channels multiplexed together.

ADCLRC is an alignment clock that controls whether left or

right channel data is present on the ADCDAT lines. ADCDAT

and ADCLRC are synchronous with the CODEC_BCLK signal,

with each data bit transition signified by a CODEC_BCLK high-

to-low transition. CODEC_BCLK can be an input or an output

depending on whether the device is in master or slave mode. See

Master and Slave Mode Operation on Page 21.

The digital audio interface also receives the digital audio data

for the internal DAC digital filters on the DACDAT input.

DACDAT is the formatted digital audio data stream output to

the DAC digital filters with left and right channels multiplexed

together. DACLRC is an alignment clock that controls whether

left or right channel data is present on DACDAT. DACDAT

and DACLRC are synchronous with the CODEC_BCLK signal

with each data bit transition signified by a CODEC_BCLK high-

to-low transition. DACDAT is always an input. CODEC_BCLK

and DACLRC are either outputs or inputs depending whether

the CODEC is in master or slave mode. See Master and Slave

Mode Operation on Page 21.

In all modes DACLRC and ADCLRC must always change on

the falling edge of CODEC_BCLK.

Left Justified Mode

Left justified mode is where the MSB is available on the first ris-

ing edge of CODEC_BCLK following a ADCLRC or DACLRC

transition.

1/f

S

DACLRC/

ADCLRC

BCLK

LEFT CHANNEL

RIGHT CHANNEL

DACDAT/

ADCDAT

1 23

MSB

n-2 n-1 n

LSB

1 23

MSB

Figure 19. Left Justified Mode

n-2 n-1 n

LSB

Rev. PrC | Page 17 of 44 | June 2008

Share Link: