ADSP-BF523C(RevPrC) 查看數據表（PDF） - Analog Devices

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ADSP-BF523C
(Rev.:RevPrC)

Blackfin® Embedded Processor

Analog Devices 

ADSP-BF523C/ADSP-BF525C/ADSP-BF527C

I2S Mode

I2S mode is where the MSB is available on the second rising edge

of CODEC_BCLK following a DACLRC or ADCLRC

transition.

1/fS

Preliminary Technical Data

DACLRC/

ADCLRC

LEFT CHANNEL

RIGHT CHANNEL

CODEC_BCLK

DACDAT/

ADCDAT

1 CODEC_BCLK

1 23

MSB

n-2 n-1 n

LSB

1 CODEC_BCLK

1 23

MSB

Figure 20. I2S Mode

Right Justified Mode

Right justified mode is where the LSB is available on the rising

edge of CODEC_BCLK preceding a DACLRC or ADCLRC

transition, yet MSB is still transmitted first.

n-2 n-1 n

LSB

1/fS

DACLRC/

ADCLRC

CODEC_BCLK

LEFT CHANNEL

RIGHT CHANNEL

DACDAT/

ADCDAT

1 23

MSB

n-2 n-1 n

LSB

1 23

MSB

Figure 21. Right Justified Mode

Frame Sync/PCM Mode

In frame sync/PCM mode, the left channel MSB is available on

either the first (mode B) or second (mode A) rising edge of

CODEC_BCLK (selectable by LRP) following a rising edge of

n-2 n-1 n

LSB

Rev. PrC | Page 18 of 44 | June 2008

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