ADSP-BF525KBCZ-6C2 查看數據表（PDF） - Analog Devices
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ADSP-BF525KBCZ-6C2 Datasheet PDF : 36 Pages
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ADSP-BF522C/ADSP-BF523C/ADSP-BF524C/ADSP-BF525C/ADSP-BF526C/ADSP-BF527C
SOFTWARE CONTROL INTERFACE
The software control interface provides access to the
programmer-selectable control registers and can operate with a
2-wire (TWI) or 3-wire (SPI) interface, depending on the setting
of the CMODE pin. If the CMODE pin is set to 0, the 2-wire
interface is selected; if 1, the 3-wire interface is selected.
Within each control register is a control data-word consisting of
16 bits, MSB first. Bit B15 to Bit B9 are the register map address,
and Bit B8 to Bit B0 are register data for the associated register
map.
When 2-wire (TWI) mode is selected, CSDA generates the serial
control data-word; CSCL clocks the serial data; and CSB deter-
mines the TWI device address. If the CSB pin is set to 0, the
address selected is 0011010; if 1, the address is 0011011.
When 3-wire (SPI) mode is selected, CSDA generates the con-
trol data-word, CSCL clocks the control data-word into the
codec, and CSB latches in the control data-word.
CSB
CSCL
CSDA B15 B14 B13 B12 B11 B10 B09 B08 B07 B06 B05 B04 B03 B02 B01 B0
REGISTER MAP
ADDRESS
REGISTER
DATA
Figure 11. Codec SPI Serial Interface
CSDA
CSCL S
1–7 8
9
START ADDR R/W ACK
1–7
8
9
SUBADDRESS ACK
1–7
8
9
DATA
ACK
Figure 12. Codec TWI Serial Interface
P
STOP
WRITE
SEQUENCE
S
A7 ... A1 A0 A(S) B15 ... B9 B8 A(S) B7 ... B0 A(S)
P
0
DEVICE
ADDRESS
REGISTER
ADDRESS
REGISTER
DATA
READ
SEQUENCE
S
A7 ... A1 A0 A(S) B15 ... B9 0
A(S)
S
A7 ... A1 A0 A(S)
B7 ... B0 A(M)
0
...
0 B8 A(M)
P
0
DEVICE
ADDRESS
REGISTER
ADDRESS
S/P = START/STOP BIT.
A0 = I2C R/W BIT.
A(S) = ACKNOWLEDGE BY SLAVE.
A(M) = ACKNOWLEDGE BY MASTER.
A(M) = ACKNOWLEDGE BY MASTER (INVERSION).
1
DEVICE
ADDRESS
REGISTER
DATA
(SLAVE DRIVE)
Figure 13. Codec TWI Write and Read Sequences
Rev. A | Page 11 of 36 | March 2010
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