ADSP-TS101SAB2Z100 查看數據表（PDF） - Analog Devices

零件编号

产品描述 (功能)

生产厂家

ADSP-TS101SAB2Z100

TigerSHARC Embedded Processor

Analog Devices 

ADSP-TS101S

The DMA controller also supports two-dimensional transfers.

The DMA controller can access and transfer two-dimensional

memory arrays on any DMA transmit or receive channel. These

transfers are implemented with index, count, and modify regis-

ters for both the X and Y dimensions.

001

000

RESET

CLOCK

REFERENCE

VOLTAGE

LINK

DEVICES

(4 MAX)

(OPTIONAL)

ADSP-TS101 #7

ADSP-TS101 #6

ADSP-TS101 #5

ADSP-TS101 #4

ADSP-TS101 #3

ADSP-TS101 #2

ADSP-TS101 #1

ID2–0

RESET

CLKS/REFS

BR7–2,0

BR1

ADDR31–0

DATA63–0

LINK

CONTROL

ADSP-TS101 #0

ID2–0

BR7–1

BR0

RESET

ADDR31–0

CLKS/REFS DATA63–0

RD

WRH/L

SCLK_P

LCLK_P

ACK

MS1–0

BUSLOCK

BMS

S/LCLK_N

VREF

LCLKRAT2–0

SCLKFREQ

CPA

DPA

BOFF

DMAR3–0

BRST

IRQ3–0

FLAG3–0

LINK

HBR

HBG

MSH

FLYBY

IOEN

LXDAT7–0

LXCLKIN

LXCLKOUT

LXDIR

TMR0E

BM

CONTROLIMP2–0

DS2–0

MSSD

RAS

CAS

LDQM

HDQM

SDWE

SDCKE

SDA10

CONTROL

ADDR

DATA

OE

GLOBAL

MEMORY

AND

WE PERIPHERALS

ACK (OPTIONAL)

CS

CS

ADDR

DATA

BOOT

EPROM

(OPTIONAL)

CLOCK

ADDR

HOST

PROCESSOR

INTERFACE

(OPTIONAL)

DATA

CS

RAS

CAS

SDRAM

MEMORY

(OPTIONAL)

DQM

WE

CKE

A10

ADDR

DATA

CLK

Figure 4. Shared Memory Multiprocessing System

The DMA controller performs the following DMA operations:

• External port block transfers. Four dedicated bidirectional

DMA channels transfer blocks of data between the DSP’s

internal memory and any external memory or memory-

mapped peripheral on the external bus. These transfers

support master mode and handshake mode protocols.

• Link port transfers. Eight dedicated DMA channels (four

transmit and four receive) transfer quad word data only

between link ports and between a link port and internal or

external memory. These transfers only use handshake

mode protocol. DMA priority rotates between the four

receive channels.

• AutoDMA transfers. Two dedicated unidirectional DMA

channels transfer data received from an external bus master

to internal memory or to link port I/O. These transfers only

use slave mode protocol, and an external bus master must

initiate the transfer.

Rev. C | Page 8 of 48 | May 2009

Share Link: