ADSP-BF538 查看數據表（PDF） - Analog Devices
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ADSP-BF538 Datasheet PDF : 56 Pages
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Preliminary Technical Data
• Non-maskable interrupt (NMI) – The NMI event can be
generated by the software watchdog timer or by the NMI
input signal to the processor. The NMI event is frequently
used as a power-down indicator to initiate an orderly shut-
down of the system.
• Exceptions – Events that occur synchronously to program
flow (the exception are taken before the instruction is
allowed to complete). Conditions such as data alignment
violations and undefined instructions cause exceptions.
• Interrupts – Events that occur asynchronously to program
flow. They are caused by input pins, timers, and other
peripherals, as well as by an explicit software instruction.
Each event type has an associated register to hold the return
address and an associated return-from-event instruction. When
an event is triggered, the state of the processors are saved on the
supervisor stack.
The ADSP-BF538/ADSP-BF538F processor’s event controllers
consist of two stages, the core event controller (CEC) and the
system interrupt controller (SIC). the core event controller
works with the system interrupt controller to prioritize and con-
trol all system events. Conceptually, interrupts from the
peripherals enter into the SIC, and are then routed directly into
the general-purpose interrupts of the CEC.
Core Event Controller (CEC)
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest)
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Event Class
Emulation/Test Control
Reset
Non-Maskable Interrupt
Exception
Reserved
Hardware Error
Core Timer
General Interrupt 7
General Interrupt 8
General Interrupt 9
General Interrupt 10
General Interrupt 11
General Interrupt 12
General Interrupt 13
General Interrupt 14
General Interrupt 15
EVT Entry
EMU
RST
NMI
EVX
—
IVHW
IVTMR
IVG7
IVG8
IVG9
IVG10
IVG11
IVG12
IVG13
IVG14
IVG15
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest priority inter-
rupts (IVG15–14) are recommended to be reserved for software
interrupt handlers, leaving seven prioritized interrupt inputs to
ADSP-BF538/ADSP-BF538F
support the peripherals of the processor. Table 2 describes the
inputs to the CEC, identifies their names in the event vector
table (EVT), and lists their priorities.
System Interrupt Controllers (SIC)
The system interrupt controllers (SIC0, SIC1) provide the map-
ping and routing of events from the many peripheral interrupt
sources to the prioritized general-purpose interrupt inputs of
the CEC. Although the ADSP-BF538/ADSP-BF538F processors
provide a default mapping, the user can alter the mappings and
priorities of interrupt events by writing the appropriate values
into the interrupt assignment registers (IAR). Table 3 describes
the inputs into the SICs and the default mappings into the CEC.
Table 3. System and Core Event Mapping
Event Source
PLL Wakeup Interrupt
DMA Controller 0 Error
DMA Controller 1 Error
PPI Error Interrupt
SPORT0 Error Interrupt
SPORT1 Error Interrupt
SPORT2 Error Interrupt
SPORT3 Error Interrupt
SPI0 Error Interrupt
SPI1 Error Interrupt
SPI2 Error Interrupt
UART0 Error Interrupt
UART1 Error Interrupt
UART2 Error Interrupt
CAN Error Interrupt
Real Time Clock Interrupts
DMA0 Interrupt (PPI)
DMA1 Interrupt (SPORT0 RX)
DMA2 Interrupt (SPORT0 TX)
DMA3 Interrupt (SPORT1 RX)
DMA4 Interrupt (SPORT1 TX)
DMA8 Interrupt (SPORT2 RX)
DMA9 Interrupt (SPORT2 TX)
DMA10 Interrupt (SPORT3 RX)
DMA11 Interrupt (SPORT3 TX)
DMA5 Interrupt (SPI0)
DMA14 Interrupt (SPI1)
DMA15 Interrupt (SPI2)
DMA6 Interrupt (UART0 RX)
DMA7 Interrupt (UART0 TX)
DMA16 Interrupt (UART1 RX)
DMA17 Interrupt (UART1 TX)
Core
Event Name
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG7
IVG8
IVG8
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG9
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
IVG10
Rev. PrD | Page 7 of 56 | May 2006
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