74HC4024-Q100 查看數據表（PDF） - Nexperia B.V. All rights reserved

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74HC4024-Q100

7-stage binary ripple counter

Nexperia B.V. All rights reserved 

Nexperia

74HC4024-Q100

7-stage binary ripple counter

6.2. Pin description

Table 2. Pin description

Symbol

CP

MR

Q6, Q5, Q4, Q3, Q2, Q2, Q1, Q0

GND

n.c.

VCC

Pin

1

2

3, 4, 5, 6, 9, 11, 12

7

8, 10, 13

14

Description

clock input (HIGH-to-LOW, edge-triggered)

master reset input (active HIGH)

parallel output

ground (0 V)

not connected

positive supply voltage

7. Functional description

Table 3. Function table

H = HIGH voltage level; L = LOW voltage level; X = don’t care; ↑ = LOW-to-HIGH clock transition;

↓ = HIGH-to-LOW clock transition.

Input

Output

MR

CP

Qn

H

X

L

L

↑

no change

↓

count

8. Limiting values

Table 4. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol

Parameter

Conditions

Min Max Unit

VCC

IIK

IOK

IO

ICC

IGND

Tstg

Ptot

supply voltage

input clamping current

output clamping current

output current

supply current

ground current

storage temperature

total power dissipation

VI < -0.5 V or VI > VCC + 0.5 V

VO < -0.5 V or VO > VCC + 0.5 V

VO = -0.5 V to VCC + 0.5 V

-0.5

-

-

-

-

-50

-65

[1] -

+7 V

±20 mA

±20 mA

±25 mA

50 mA

- mA

+150 °C

500 mW

[1] For SO16 package: Ptot derates linearly with 8 mW/K above 70 °C.

74HC4024_Q100

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 2 — 23 November 2018

© Nexperia B.V. 2018. All rights reserved

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