74HC4024-Q100 查看數據表（PDF） - Nexperia B.V. All rights reserved
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74HC4024-Q100 Datasheet PDF : 13 Pages
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Nexperia
74HC4024-Q100
7-stage binary ripple counter
11.1. Waveforms and test circuit
MR input
VM
CP input
tW
1/fmax
trec
VM
Fig. 6.
tPHL
tW
tPLH
tPHL
Q0 or Qn
output
10 %
90 %
90 %
VM
10 %
tTLH
tTHL
001aab910
Also showing the master reset (MR) pulse width, the master reset to output (Qn) propagation delays and the
master reset to clock (CP) recovery time.
VM = 0.5 x VCC.
Waveforms showing the clock (CP) to output (Qn) propagation delays, the clock pulse width, the output
transition times and the maximum clock frequency
VI 90 %
negative
pulse
GND
VI
positive
pulse
GND 10 %
VM
10 %
tf
tr
90 %
VM
G
VI
RT
tW
tW
VCC
DUT
VM
tr
tf
VM
VO
CL
001aah768
Fig. 7.
Test data is given in Table 8.
Definitions for test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
Test circuit for measuring switching times
Table 8. Test data
Supply
VCC
2.0 V
4.5 V
6.0 V
5.0 V
Input
VI
VCC
VCC
VCC
VCC
tr, tf
6 ns
6 ns
6 ns
6 ns
Load
CL
50 pF
50 pF
50 pF
15 pF
74HC4024_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 23 November 2018
© Nexperia B.V. 2018. All rights reserved
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