AT91RM9200(2003) 查看數據表（PDF） - Atmel Corporation

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AT91RM9200
(Rev.:2003)

ARM920T™- based Microcontroller

Atmel Corporation 

Burst Flash

Controller

Peripheral Data

Controller

Advanced

Interrupt

Controller

1768B–ATARM–08/03

AT91RM9200

– Multibank Ping-pong Access

– Timing parameters specified by software

– Automatic refresh operation, refresh rate is programmable

• Energy-saving capabilities

– Self-refresh and Low-power Modes supported

• Error detection

– Refresh Error Interrupt

• SDRAM Power-up Initialization by software

• Latency is set to two clocks (CAS Latency of 1, 3 Not Supported)

• Auto Precharge Command not used

• Multiple Access Modes supported

– Asynchronous or Burst Mode Byte, Half-word or Word Read Accesses

– Asynchronous Mode Half-word Write Accesses

• Adaptability to different device speed grades

– Programmable Burst Flash Clock Rate

– Programmable Data Access Time

– Programmable Latency after Output Enable

• Adaptability to different device access protocols and bus interfaces

– Two Burst Read Protocols: Clock Control Address Advance or Signal Controlled

Address Advance

– Multiplexed or separate address and data buses

– Continuous Burst and Page Mode Accesses supported

• Generates transfers to/from peripherals such as DBGU, USART, SSC, SPI and MCI

• Twenty channels

• One Master Clock cycle needed for a transfer from memory to peripheral

• Two Master Clock cycles needed for a transfer from peripheral to memory

• Controls the interrupt lines (nIRQ and nFIQ) of an ARM® Processor

• Thirty-two individually maskable and vectored interrupt sources

– Source 0 is reserved for the Fast Interrupt Input (FIQ)

– Source 1 is reserved for system peripherals (ST, RTC, PMC, DBGU…)

– Source 2 to Source 31 control thirty embedded peripheral interrupts or external

interrupts

– Programmable Edge-triggered or Level-sensitive Internal Sources

– Programmable Positive/Negative Edge-triggered or High/Low Level-sensitive

External Sources

• 8-level Priority Controller

– Drives the Normal Interrupt of the processor

– Handles priority of the interrupt sources 1 to 31

– Higher priority interrupts can be served during service of lower priority interrupt

• Vectoring

– Optimizes Interrupt Service Routine Branch and Execution

7

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