M41T62LC6F(2019) 查看數據表（PDF） - STMicroelectronics

零件编号

产品描述 (功能)

生产厂家

M41T62LC6F
(Rev.:2019)

Low-power serial real-time clocks (RTCs) with alarm

STMicroelectronics 

M41T62, M41T64, M41T65

Operation

2

2.1

2.1.1

2.1.2

2.1.3

2.1.4

Operation

The M41T6x clock operates as a slave device on the serial bus. Access is obtained by implementing a start

condition followed by the correct slave address (D0h). The 16 bytes contained in the device can then be accessed

sequentially in the following order:

• 1st byte: tenths/hundredths of a second register

• 2nd byte: seconds register

• 3rd byte: minutes register

• 4th byte: hours register

• 5th byte: square wave/day register

• 6th byte: date register

• 7th byte: century/month register

• 8th byte: year register

• 9th byte: calibration register

• 10th byte: watchdog register

• 11th - 15th bytes: alarm registers

• 16th byte: flags register

2-wire bus characteristics

The bus is intended for communication between different ICs. It consists of two lines: a bi-directional data signal

(SDA) and a clock signal (SCL). Both the SDA and SCL lines must be connected to a positive supply voltage via a

pull-up resistor.

The following protocol has been defined:

• Data transfer may be initiated only when the bus is not busy.

• During data transfer, the data line must remain stable whenever the clock line is high.

• Changes in the data line, while the clock line is high, will be interpreted as control signals.

Accordingly, the following bus conditions have been defined.

Bus not busy

Both data and clock lines remain high.

Start data transfer

A change in the state of the data line, from high to low, while the clock is high, defines the START condition.

Stop data transfer

A change in the state of the data line, from low to high, while the clock is high, defines the STOP condition.

Data valid

The state of the data line represents valid data when after a start condition, the data line is stable for the duration

of the high period of the clock signal. The data on the line may be changed during the Low period of the clock

signal. There is one clock pulse per bit of data.

Each data transfer is initiated with a start condition and terminated with a stop condition. The number of data

bytes transferred between the start and stop conditions is not limited. The information is transmitted byte-wide

and each receiver acknowledges with a ninth bit.

By definition a device that gives out a message is called “transmitter,” the receiving device that gets the message

is called “receiver.” The device that controls the message is called “master.” The devices that are controlled by the

master are called “slaves.”

DS3840 - Rev 24

page 7/42

Share Link: