74HC163 查看數據表（PDF） - Nexperia B.V. All rights reserved

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74HC163

Presettable synchronous 4-bit binary counter; synchronous reset

Nexperia B.V. All rights reserved 

Nexperia

74HC163; 74HCT163

Presettable synchronous 4-bit binary counter; synchronous reset

Symbol Parameter Conditions

CPD

power

VI = GND to VCC - 1.5 V;

dissipation VCC = 5 V; fi = 1 MHz

capacitance

25 °C

-40 °C to +85 °C

Min Typ Max Min Max

[3] - 35 -

-

-

-40 °C to +125 °C Unit

Min

Max

-

- pF

[1] tpd is the same as tPHL and tPLH.

[2] tt is the same as tTHL and tTLH.

[3] CPD is used to determine the dynamic power dissipation (PD in μW):

PD = CPD x VCC2 x fi x N + ∑(CL x VCC2 x fo) where:

fi = input frequency in MHz;

fo = output frequency in MHz;

CL = output load capacitance in pF;

VCC = supply voltage in V;

N = number of inputs switching;

∑(CL x VCC2 x fo) = sum of outputs.

10.1. Waveforms and test circuit

VI

CP input

1/fmax

VM

GND

tW

tPHL

tPLH

Fig. 9.

VOH

Qn, TC

output

VOL

90 %

VM

10 %

tTHL

10 %

90 %

tTLH

aaa-012353

Measurement points are given in Table 8.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

The clock (CP) to outputs (Qn, TC) propagation delays, pulse width, output transition times and maximum

frequency

VI

CET input

VM

GND

VOH

tPLH

90 %

tPHL

90 %

TC output

VOL

10 %

VM

tTLH

10 %

tTHL

aaa-012354

Measurement points are given in Table 8.

Logic levels VOL and VOH are typical output voltage levels that occur with the output load.

Fig. 10. The count enable carry input (CET) to terminal count output (TC) propagation delays and output transition

times

74HC_HCT163

Product data sheet

All information provided in this document is subject to legal disclaimers.

Rev. 5 — 12 October 2018

© Nexperia B.V. 2018. All rights reserved

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