74HC163-Q100 查看數據表（PDF） - Nexperia B.V. All rights reserved
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74HC163-Q100
Nexperia B.V. All rights reserved
74HC163-Q100 Datasheet PDF : 19 Pages
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5. Pinning information
74HC163-Q100; 74HCT163-Q100
Presettable synchronous 4-bit binary counter; synchronous reset
5.1. Pinning
74HC163
74HCT163
MR 1
16 VCC
CP 2
15 TC
D0 3
14 Q0
D1 4
13 Q1
D2 5
12 Q2
D3 6
11 Q3
CEP 7
10 CET
GND 8
9 PE
aaa-012181
Fig. 5. Pin configuration SOT109-1 (SO16)
74HC163
74HCT163
MR 1
CP 2
D0 3
D1 4
D2 5
D3 6
CEP 7
GND 8
16 VCC
15 TC
14 Q0
13 Q1
12 Q2
11 Q3
10 CET
9 PE
aaa-012182
Fig. 6. Pin configuration SOT403-1 (TSSOP16)
5.2. Pin description
Table 2. Pin description
Symbol
MR
CP
D0, D1, D2, D3
CEP
GND
PE
CET
Q0, Q1, Q2, Q3
TC
VCC
Pin
1
2
3, 4, 5, 6
7
8
9
10
14, 13, 12, 11
15
16
Description
synchronous master reset (active LOW)
clock input (LOW-to-HIGH, edge triggered)
data input
count enable input
ground (0 V)
parallel enable input (active LOW)
count enable carry input
flip-flop output
terminal count output
supply voltage
74HC_HCT163_Q100
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 2 — 12 October 2018
© Nexperia B.V. 2018. All rights reserved
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