MB39C022N 查看數據表（PDF） - Cypress Semiconductor

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MB39C022N

Buck DC/DC Converter + Low Noise LDO

Cypress Semiconductor 

MB39C022G/J/L/N

5. Function Descriptions

5.1 PFM/PWM Logic Control Block (CH1)

The built-in P-ch and N-ch MOS FETs are controlled for synchronization rectification according to the frequency (2.0 MHz) oscillated

from the built-in oscillator (square wave oscillation circuit). Under light load, it operates intermittently.

This circuit protects the through current caused by synchronous rectification and the reverse current in Discontinuous Conduction

Mode.

Since the PWM control circuit of this IC is in the control method in current mode, the current peak value is monitored and controlled

as required.

5.2 Level Converter and Iout Comparator Circuit (CH1)

The Level converter circuit detects the current (ILX) which flows to the external inductor from the built-in P-ch MOS FET. By comparing

VIDET obtained through I-V conversion of peak current IPK of ILX with the Error Amp. output, the Iout Comparator turns off the built-in

P-ch MOS FET via the PWM Logic Control circuit.

5.3 Error Amp. Circuit (CH1)

The error amplifier (Error Amp.) detects the output voltage from the DC/DC converter and output to the current comparators (ICOMP).

The output voltage setting resistor externally connected to FB allows an arbitrary output voltage to be set.

5.4 LDO Block (CH2)

The integrated low noise low dropout regulator (LDO) is available up to 300 mA current capability and 700 mA over current protection

(OCP) 350 mA short circuit protection (SCP). The LDO output VOUT2 requires a 4.7 μF capacitor for MB39C022G and MB39C022N

and a 1.0 μF capacitor for MB39C022J and MB39C022L for stability. MB39C022G, MB39C022J, MB39C022L and MB39C022N have

fixed 3.3 V, 2.85 V, 1.8 V and 1.2 V output voltages respectively, eliminating the need for an external resistor divider.

5.5 POR Block

The POR circuit monitors the VO1 through the FB pin voltage. When the FB pin voltage reaches 97% of VFBTH, POR pin becomes

high level after the hold time of 66 ms. The POR pin is an open-drain output and pulled up to VIN or VO1 with an external resistor.

Timing Chart : (POR Pin Pulled up to VIN With Resistor)

VUVLO

VIN

EN1

FB

VTH × 97%

POR

thold

thold

VUVLO : UVLO threshold voltage (VTLH = 2.050 V)

VTH : FB pin threshold voltage (VTH = 0.3 V)

5.6 Reference Voltage Block (VREF)

A high accuracy reference voltage is generated with BGR (bandgap reference) circuit.

Document Number: 002-08460 Rev. *C

Page 7 of 29

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