S-25C040A0H-T8T2UD 查看數據表（PDF） - Unspecified

零件编号

产品描述 (功能)

生产厂家

S-25C040A0H-T8T2UD

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE

Unspecified 

Rev.3.0_01_C

105°C OPERATION SPI SERIAL E2PROM FOR AUTOMOTIVE

S-25C010A/020A/040A H Series

 Operation

1. Status register

The status register’s organization is below. The status register can Write and Read by a specific instruction.

b7

b6

b5

b4

b3

b2

b1

b0

1

1

1

1

BP1

BP0

WEL

WIP

Block Protect

Write Enable Latch

Write In Progress

Figure 10 Organization of Status Register

The status/control bits of the status register are as follows.

1.1 BP1, BP0 (b3, b2) : Block protect

Bit BP1 and BP0 are composed of the nonvolatile bit. The area size of Software Protect with respect to WRITE

instructions is defined by the BP1 and BP0 bits. Rewriting these bits is possible by the WRSR instruction. To protect

the memory area against the WRITE instruction, set either or both of bit BP1 and BP0 to “1”. Rewriting bit BP1 and

BP0 is possible unless they are in Hardware Protect mode.

Refer to “ Protect Operation” for details of “Block Protect”.

1.2 WEL (b1) : Write enable latch

Bit WEL shows the status of internal Write Enable Latch. Bit WEL is set by the WREN instruction only. If bit WEL is

“1”, this is the status that Write Enable Latch is set. If bit WEL is “0”, Write Enable Latch is in reset, so that the

S-25C010A/020A/040A does not receive the WRITE or WRSR instruction. Bit WEL is reset after these operations;

 The power supply voltage is dropping

 Power-on

 After performing WRDI

 After the Write operation by the WRSR instruction

 After the Write operation by the WRITE instruction

 After setting the WP pin to “L”

11

Share Link: