A8837 查看數據表（PDF） - Allegro MicroSystems

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A8837

Photoflash Capacitor Charger with IGBT Driver

Allegro MicroSystems 

A8837

Photoflash Capacitor Charger with IGBT Driver

Leakage Inductance and Secondary Capacitance. The trans-

former design should minimize the leakage inductance to ensure

the turn-off voltage spike at the SW node does not exceed the 40 V

limit. An achievable minimum leakage inductance for this applica-

tion, however, is usually compromised by an increase in parasitic

capacitance. Furthermore, the transformer secondary capacitance

should be minimized. Any secondary capacitance is multiplied by

N 2 when reflected to the primary, leading to high initial current

swings when the switch turns on, and to reduced efficiency.

Adjusting Output Voltage

The A8436 senses output voltage during switch off-time. This

allows the voltage divider network, R1 through R3, to be con-

nected at the anode of the high voltage output diode, D1, elimi-

nating power loss due to the feedback network when charging is

complete. The output voltage can be adjusted by selecting proper

values of the voltage divider resistors. Use the following equation

to calculate values for Rx (Ω):

R1 + R2 = VOUT − 1 .

(3)

R3

VFB

R1 and R2 together need to have a breakdown voltage of at least

300 V. A typical 1206 surface mount resistor has a 150 V break-

down voltage rating. It is recommended that R1 and R2 have

similar values to ensure an even voltage stress between them.

Recommended values are:

R1 = R2 = 150 kΩ (1206)

R3 = 1.2 kΩ (0603)

which together yield a stop voltage of 303 V. Using higher

resistance values for R1, R2, and R3 does not offer significant

efficiency improvement, because the power loss of the feedback

network occurs mainly during switch off-time, and because the

off-time is only a small fraction of each charging cycle.

Output Diode Selection

Choose the rectifying diode(s), D1, to have small parasitic

capacitance (short reverse recovery time) while satisfying the

reverse voltage and forward current requirements.

The peak reverse voltage of the diode, VD_Peak , occurs when the

internal MOSFET switch is closed, and the primary-side current

starts to ramp-up. It can be calculated as:

VD_Peak= VOUT + N ×VBATT .

(4)

The peak current of the rectifying diode, ID_Peak, is calculated as:

/ ID_Peak = IPrimary_Peak N .

(5)

Input Capacitor Selection

Ceramic capacitors with X5R or X7R dielectrics are recom-

mended for the input capacitor, C2. It should be rated at least

4.7 μF / 6.3 V to decouple the battery input, VBATT , at the primary

of the transformer. When using a separate bias, VBIAS , for the

A8837 VIN supply, connect at least a 0.1 μF / 6.3 V bypass

capacitor to the VIN pin.

Layout Guidelines

Key to a good layout for the photoflash capacitor charger circuit

is to keep the parasitics minimized on the power switch loop

(transformer primary side) and the rectifier loop (secondary side).

Use short, thick traces for connections to the transformer primary

and SW pin.

Output voltage sensing circuit elements must be kept away from

switching nodes such as SW pin. Make sure that there is no

ground plane underneath R1 and R2, because parasitic capaci-

tance to ground will affect sensing accuracy. It is important that

the ¯D¯¯O¯¯N¯¯E¯ signal trace and other signal traces be routed away

from the transformer and other switching traces, in order to mini-

mize noise pickup. In addition, high voltage isolation rules must

be followed carefully to avoid breakdown failure of the circuit

board.

Allegro MicroSystems, Inc.

10

115 Northeast Cutoff, Box 15036

Worcester, Massachusetts 01615-0036 (508) 853-5000

www.allegromicro.com

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