DS3514TR 查看數據表（PDF） - Maxim Integrated

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DS3514TR

I2C Gamma and VCOM Buffer with EEPROM

Maxim Integrated 

I2C Gamma and VCOM Buffer with EEPROM

Detailed Description

The DS3514 operates in one of three modes that deter-

mine how the VCOM and gamma DACs are

controlled/updated. The first two modes allow “banked”

control of the 14 gamma channels and one VCOM chan-

nel. Depending on the mode, one of four banks (in

EEPROM) can be selected using either the S0/S1 pins

or using the SOFT S0/S1 bits in the Soft S0/S1 register.

Once a bank is selected, the LD pin can then be used

to simultaneously update each channel’s DAC output.

The third and final mode is not banked. It allows I2C

control of each channel’s Latch A register that is SRAM

(volatile), allowing quick and unlimited updates. In this

mode, the LD pin can also be used to simultaneously

update each channel’s DAC output. A detailed descrip-

tion of the three modes as well as additional features of

the DS3514 follows.

Mode Selection

The DS3514 mode of operation is determined by two

bits located in Control register (CR, register 48h), which

is nonvolatile (NV) (EEPROM). In particular, the mode is

determined by the MODE0 bit (CR.0) and the MODE1

bit (CR.1). Table 1 illustrates how the two control bits

are used to select the operating mode. When shipped

from the factory, the DS3514 is programmed with both

MODE bits set to zero.

S0/S1 Pin-Controlled Bank-Updating Mode

As shown in the Block Diagram, each channel contains

four words of EEPROM that are used to implement the

“banking” functionality. Each bank contains unique

DAC settings for each channel. When the DS3514 is

configured in this operating mode, the desired bank is

selected using the S0 and S1 pins as shown in Table 2

where 0 is ground and 1 is VCC. For example, if S0 and

S1 are both connected to ground, the first bank (Bank

A) is selected. Once a bank is selected, the timing of

the DAC update depends on the state of LD pin. When

LD is high, Latch B functions as a flow-through latch, so

the amplifier responds asynchronously to changes in

Table 1. Operating Modes

MODE1 BIT

(CR.1)

0

0

1

MODE0 BIT

(CR.0)

MODE

0

S0/S1 Pin-Controlled Bank

Updating (Factory Default)

1

S0/S1 Bit-Controlled Bank

Updating

X

I2C Individual Channel

Control

the state of S0/S1 to meet the tSEL specification.

Conversely, when LD is low, Latch B functions as a

latch, holding its previous data. A low-to-high transition

on LD allows the Latch B input data to flow through and

update the DACs with the EEPROM bank selected by

S0/S1. A high-to-low transition on LD latches the select-

ed DAC data into Latch B.

SOFT S0/S1 Bit-Controlled Bank-Updating

Mode

This mode also features banked operation with the only

difference being how the desired bank is selected. In

particular, the bank is selected using the SOFT S0 (bit

0) and SOFT S1 (bit 1) bits contained in the Soft S0/S1

register (40h). The S0 and S1 pins are ignored in this

mode. Table 2 illustrates the relationship between the

bit settings and the selected bank. For example, if

SOFT S0 and SOFT S1 are written to zero, the first bank

(Bank A) is selected. Once a bank is selected, the tim-

ing of the DAC update depends on the state of the LD

pin. When LD is high, Latch B functions as a flow-

through latch, so the amplifier responds asynchronous-

ly to changes in the state of the SOFT S0/S1 bits. These

are changed by an I2C write. Conversely, when LD is

low, Latch B functions as a latch, holding its previous

data. A low-to-high transition on LD allows the Latch B

input data to flow through and update the DACs with

the EEPROM bank selected by the SOFT S0/S1 bits. A

high-to-low transition on LD latches the selected DAC

data into Latch B.

Because the Soft S0/S1 register is SRAM, subsequent

power ups result in the SOFT S0 and SOFT S1 bits

being cleared to 0 and, hence, powering up to Bank A.

I2C Individual Channel-Control Mode

In this mode the I2C master writes directly to individual

channel Latch A registers to update a single DAC (i.e.,

not banked). The Latch A registers are SRAM and not

EEPROM. This allows an unlimited number of write

cycles as well as quicker write times since tW only

applies to EEPROM writes. As shown in the Memory

Table 2. Bank Selection Table

BIT OR PIN

S1

S0

0

0

0

1

1

0

1

1

VCOM

CHANNEL

VCOM Bank A

VCOM Bank B

VCOM Bank C

VCOM Bank D

GAMMA

CHANNELS

GM1–GM14 Bank A

GM1–GM14 Bank B

GM1–GM14 Bank C

GM1–GM14 Bank D

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