VSC8184(2002) 查看數據表（PDF） - Vitesse Semiconductor
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VSC8184 Datasheet PDF : 2 Pages
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VSC8184
11.5-12.5Gb/s 1:16 Demultiplexer with Clock Recovery
GENERAL DESCRIPTION:
The VCS8184 combines a clock recovery unit and data
retiming with a 1:16 Demultiplexer on a single chip to
directly generate 16-bit wide data from an incoming
11.5Gb/s to 12.5Gb/s data stream, for use in SONET STS-
192/SDH STM-64 systems. An on-chip Phase Locked Loop
(PLL) with Voltage Controlled Oscillator (VCO) generates a 11.5GHz to 12.5GHz
clock, which remains phase locked to the incoming data. The incoming data is
retimed and Demultiplexer into 16 parallel outputs. It features a highly flexible
reference clock input scheme. The user can select between 22-24 MHz, 180-
195MHz or 719-781MHz LVPECL reference clock inputs. The input serial data
sampling point voltage threshold can be adjusted. Additional features include a
parity bit (PARITY±) that is clocked out with the 16 parallel data, Bit Order Swap
(BITORDER) and Data Polarity Invert (DINVERT). To assist in monitoring device
operation a Loss-of-Lock (LOLN) alarm and no reference clock (NOREFN) alarm
are provided. The device is packaged in a modified 90-ball, Ball Grid Array (BGA).
VSC8184 BLOCK DIAGRAM:
SPECIFICATIONS:
11.5 to 12.5 Gb/s Continuous Lock-Range Operation
10 mV Input Sensitivity
Supply Voltage: 3.3V (Typ)
Total Power Dissipation: 1.6W (Typ)
15x15mm Low Profile 90 Ball TBGA (Taped BGA)
Package
Operating Temperature Range: 0°C to +85°C (case)
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©2002 Vitesse Semiconductor Corporation
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