MAX6319LHUK46C-T 查看數據表（PDF） - Maxim Integrated

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MAX6319LHUK46C-T

5-Pin µP Supervisory Circuits with Watchdog and Manual Reset

Maxim Integrated 

5-Pin µP Supervisory Circuits with

Watchdog and Manual Reset

P-channel transistor on-resistance quickly charges

stray capacitance on the reset line, allowing RESET to

transition from low to high within the required two elec-

tronic-clock cycles, even with several devices on the

reset line. This process occurs regardless of whether

the reset was caused by VCC dipping below the reset

threshold, the watchdog timing out, MR being asserted,

or the µP or other device asserting RESET. The parts do

not require an external pull-up. To minimize supply cur-

rent consumption, the internal 4.7kΩ pull-up resistor

disconnects from the supply whenever the MAX6316M/

MAX6318MH/MAX6319MH assert reset.

Open-Drain RESET Output

The MAX6320P/MAX6321HP/MAX6322HP have an

active-low, open-drain reset output. This output struc-

ture will sink current when RESET is asserted. Connect

a pull-up resistor from RESET to any supply voltage up

to 6V (Figure 6). Select a resistor value large enough to

VCC

RESET

tRP

OR

0.7V

µC RESET DELAY

tS

0.8 x VCC

tR

RESET PULLED LOW

BY µC OR

RESET GENERATOR

ACTIVE

PULL-UP

TURNS ON

Figure 5. Bidirectional RESET Timing Diagram

+3.3V

VCC

MR*

WDI**

RESET***

10k

RESET

+5.0V

5V SYSTEM

MAX6320

MAX6321

MAX6322

GND

* MAX6320/MAX6322

** MAX6320/MAX6321

*** MAX6321/MAX6322

Figure 6. MAX6320P/MAX6321HP/MAX6322HP Open-Drain

RESET Output Allows Use with Multiple Supplies

register a logic low (see Electrical Characteristics), and

small enough to register a logic high while supplying all

input current and leakage paths connected to the RESET

line. A 10kΩ pull-up is sufficient in most applications.

Manual-Reset Input

The MAX6316_/MAX6317H/MAX6319_H/MAX6320P/

MAX6322HP feature a manual-reset input. A logic low on

MR asserts a reset. After MR transitions low to high, reset

remains asserted for the duration of the reset timeout peri-

od (tRP). The MR input is connected to VCC through an

internal 52kΩ pull-up resistor and therefore can be left

unconnected when not in use. MR can be driven with

TTL-logic levels in 5V systems, with CMOS-logic levels in

3V systems, or with open-drain or open-collector output

devices. A normally-open momentary switch from MR to

ground can also be used; it requires no external

debouncing circuitry. MR is designed to reject fast,

negative-going transients (typically 100ns pulses). A

0.1µF capacitor from MR to ground provides additional

noise immunity.

The MR input pin is equipped with internal ESD-protection

circuitry that may become forward biased. Should MR be

driven by voltages higher than VCC, excessive current

would be drawn, which would damage the part. For

example, assume that MR is driven by a +5V supply other

than VCC. If VCC drops lower than +4.7V, MR’s absolute

maximum rating is violated [-0.3V to (VCC + 0.3V)], and

undesirable current flows through the ESD structure from

MR to VCC. To avoid this, use the same supply for MR as

the supply monitored by VCC. This guarantees that the

voltage at MR will never exceed VCC.

Watchdog Input

The MAX6316_/MAX6317H/MAX6318_H/MAX6320P/

MAX6321HP feature a watchdog circuit that monitors

the µP’s activity. If the µP does not toggle the watchdog

input (WDI) within the watchdog timeout period (tWD),

reset asserts. The internal watchdog timer is cleared by

reset or by a transition at WDI (which can detect pulses

as short as 50ns). The watchdog timer remains cleared

while reset is asserted. Once reset is released, the

timer begins counting again (Figure 7).

The WDI input is designed for a three-stated output

device with a 10µA maximum leakage current and the

capability of driving a maximum capacitive load of 200pF.

The three-state device must be able to source and sink at

least 200µA when active. Disable the watchdog function

by leaving WDI unconnected or by three-stating the driver

connected to WDI. When the watchdog timer is left open

circuited, the timer is cleared internally at intervals equal

to 7/8 of the watchdog period.

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