MAX697MJE 查看數據表（PDF） - Maxim Integrated

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MAX697MJE

Microprocessor Supervisory Circuits

Maxim Integrated 

MAX696/MAX697

Microprocessor Supervisory Circuits

Pin Description (continued)

PIN

MAX696

MAX697

—

1

—

12

—

13

NAME

TEST

CE OUT

CE IN

FUNCTION

Used During Maxim Manufacture Only. Always ground this pin.

CE OUT goes low only when CE IN is low and LLIN is above 1.3V. See Figure 5.

The Input to the CE Gating Circuit. Connect to GND or VOUT if not used.

+5V

VCC

INPUT

0.1µF

3V

BATTERY

3

1

VCC

VBATT

9

PFI

5

BATT ON

0.1µF

2

VOUT

CMOS

RAM

MAX696

4

GND

NO CONNECTION

RESET

7

OSC IN

8

OSC SEL

13

LLIN

LOW LINE

6

WDO

14

11

WDI

10

PFO

15

RESET

18

RESET

AUDIBLE

ALARM

A0–A15

I/O

NMI

RESET

MICROPROCESSOR

OTHER SYSTEM RESET SOURCES

Figure 1. MAX696 Typical Application

SYSTEM STATUS INDICATORS

Typical Applications

MAX696

A typical connection for the MAX696 is shown in

Figure 1. CMOS RAM is powered from VOUT. VOUT

is internally connected to VCC when power is present,

or to VBATT when VCC is less than the battery voltage.

VOUT can supply 50mA from VCC, but if more current is

required, an external pnp transistor can be added. When

VCC is higher than VBATT, the BATT ON output goes

low, providing 7mA of base drive for the external transis-

tor. When VCC is lower than VBATT, an internal 200Ω

MOSFET connects the backup battery to VOUT. The qui-

escent current in the battery-backup mode is 1μA maxi-

mum when VCC is between 0V and (VBATT - 700mV).

Reset Output

A voltage detector monitors VCC and generates a RESET

output to hold the microprocessor’s RESET line low when

LLIN is below 1.3V. An internal monostable holds RESET

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