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MAX697MJE

Microprocessor Supervisory Circuits

Maxim Integrated 

MAX696/MAX697

Microprocessor Supervisory Circuits

The MAX696 operates with battery voltages from 2.0V

to 4.25V. The battery voltage should not be within 0.5V

of VCC, or switchover may occur. High-value capacitors,

either standard electrolytic or the farad-size double-

layer capacitors, can also be used for short-term memory

backup. The capacitor charging voltage should include a

diode to limit the fully charged voltage to approximately

0.5V less than VCC. The charging resistor for recharge-

able batteries should be connected to VOUT since this

eliminates the discharge path that exists if the resistor is

connected to VCC.

A small leakage current of typically 10nA (20nA max)

flows out of the VBATT terminal. This current varies with

the amount of current that is drawn from VOUT, but its

polarity is such that the backup battery is always slightly

charged, and is never discharged while VCC is in its

operating voltage range. This extends the shelf life of the

backup battery by compensating for its self-discharge cur-

rent. Also note that this current poses no problem when

lithium batteries are used for backup since the maximum

current (20nA) is safe for even the smallest lithium cells.

If the battery-switchover section is not used, connect

VBATT to GND and connect VOUT to VCC. Table 2 shows

the state of the inputs and output in the lowpower battery-

backup mode.

Reset Output

RESET is an active-low output that goes low whenever

LLIN falls below 1.3V. It remains low until LLIN rises above

1.312V for 50ms. (See Figures 4 and 5.)

The guaranteed minimum and maximum low-line thresh-

olds of the MAX696/MAX697 are 1.25V and 1.35V. The

LLIN comparator has approximately 12mV of hysteresis.

The response time of the reset voltage comparator is

about 100μs. LLIN should be bypassed to ensure that

glitches do not activate the RESET output.

RESET also goes low if the watchdog timer is enabled and

WDI remains either high or low longer than the watchdog

timeout period. RESET has an internal 3μA pullup, and

can either connect to an open-collector reset bus or direct-

ly drive a CMOS gate without an external pullup resistor.

(MAX697) CE IN

VCC

CE OUT (MAX697)

LOW LINE

POWER-ON

RESET

LLIN

+

-

RESET

RESET

TIME

Qn

WATCHDOG

1.3V

FROM

WATCHDOG

TIMER

Figure 4. Reset Block Diagram

RESET

RESET

10kHz CLOCK

FROM TIMEBASE

SECTION

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