MAX793(1996) 查看數據表（PDF） - Maxim Integrated
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MAX793 Datasheet PDF : 20 Pages
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3.0V/3.3V Adjustable Microprocessor
Supervisory Circuits
______________________________________________________________Pin Description
PIN
MAX793/
MAX794
MAX795
NAME
FUNCTION
Supply Output for CMOS RAM. When VCC rises above the reset threshold or above
1
1
OUT
VBATT, OUT is connected to VCC through an internal P-channel MOSFET switch. When
VCC falls below VSW and VBATT, BATT connects to OUT.
2
2
VCC
Main Supply Input
BATT OK Battery Status Output. High in normal operating mode when VBATT exceeds VBOK, other-
(MAX793) wise low. VBATT is checked continuously. Disabled and logic low while VCC is below VSW.
3
—
RESET IN Reset Input. Connect to an external resistor divider to select the reset threshold. The
(MAX794) reset threshold can be programmed anywhere in the VSW to 5.5V range.
Power-Fail Comparator Input. When PFI is less than VPFT or when VCC falls below VSW,
4
—
PFI
PFO goes low; otherwise, PFO remains high (see Power-Fail Comparator section).
Connect to VCC if unused.
Logic Output/External Bypass Switch-Driver Output. High when OUT switches to BATT.
5
3
BATT ON Low when OUT switches to VCC. Connect the base/gate of PNP/PMOS transistor to
BATT ON for IOUT requirements exceeding 75mA.
6
4
GND
Ground
Power-Fail Comparator Output. When PFI is less than VPFT or when VCC falls below
7
—
PFO
VSW, PFO goes low; otherwise, PFO remains high. PFO is also used to enable the bat-
tery freshness seal (see Battery Freshness Seal, and Power-Fail Comparator sections).
Manual Reset Input. A logic low on MR asserts reset. Reset remains asserted as long as
8
—
MR
MR is low and for 200ms after MR returns high. The active-low input has an internal
70µA pull-up current. In can be driven from a TTL- or CMOS-logic line or shorted to
ground with a switch. Leave open if unused.
Watchdog Output. WDO goes low if WDI remains either high or low for longer than the
9
—
WDO
watchdog timeout period. WDO returns high on the next transition of WDI. WDO is a
logic high for VSW < VCC < VRST, and low when VCC is below VSW.
Watchdog Input. If WDI remains either high or low for longer than the watchdog timeout
10
—
WDI
period, the internal watchdog timer runs out and WDO goes low. WDO returns high on
the next transition of WDI. Connect WDO to MR to generate a reset due to a watchdog
fault.
11
5
CE IN
Chip-Enable Input. The input to the chip-enable gating circuit. Connect to GND if unused
Chip-Enable Output. CE OUT goes low only when CE IN is low and reset is not asserted.
12
6
CE OUT If CE IN is low when reset is asserted, CE OUT will remain low for 10µs or until CE IN
goes high, whichever occurs first. CE OUT is pulled up to OUT.
13
—
RESET
Active-High Reset Output. Sources and sinks current. RESET is the inverse of RESET.
14
—
LOWLINE
Early Power-Fail Warning Output. Low when VCC falls to VLR. This output can be used to
generate an NMI to provide early warning of imminent power-failure.
Open-Drain, Active-Low Reset Output. Pulses low for 200ms when triggered, and stays
15
7
RESET
low whenever VCC is below the reset threshold or when MR is a logic low. It remains low
for 200ms after either VCC rises above the reset threshold, the watchdog triggers a reset
(WDO connected to MR), or MR goes low to high.
Backup-Battery Input. When VCC falls below VSW and VBATT, OUT switches from VCC to
16
8
BATT
BATT. When VCC rises above the reset threshold or above VBATT, OUT reconnects to
VCC. VBATT may exceed VCC. Connect VCC, OUT, and BATT together if no battery is
used.
_______________________________________________________________________________________ 7
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