MAX795 查看數據表（PDF） - Maxim Integrated

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MAX795

3.0V/3.3V Adjustable Microprocessor Supervisory Circuits

Maxim Integrated 

3.0V/3.3V Adjustable Microprocessor

Supervisory Circuits

brownout conditions. RESET is guaranteed to be a

logic low for 0V < VCC < VRST, provided VBATT is

greater than 1V. Without a backup battery (VBATT =

VCC = VOUT), RESET is guaranteed valid for VCC ≥ 1V.

Once VCC exceeds the reset threshold, an internal

timer keeps RESET low for the reset timeout period

(tRP); after this interval, RESET becomes high imped-

ance (Figure 2). RESET is an open-drain output, and

requires a pullup resistor to VCC (Figure 3). Use a

4.7kΩ to 1MΩ pullup resistor that provides sufficient

current to assure the proper logic levels to the µP.

If a brownout condition occurs (VCC dips below the

reset threshold), RESET goes low. Each time RESET is

asserted, it stays low for the reset timeout period. Any

time VCC goes below the reset threshold, the internal

timer restarts.

The watchdog output (WDO) can also be used to initi-

ate a reset. See the Watchdog Output section.

The RESET output is the inverse of the RESET output,

and it can both source and sink current.

VLL VRST

VCC

VSW

VLOWLINE

(MAX793/MAX794)

4µs

VRESET

20µs

(RESET PULLED UP TO VCC)

VRESET

20µs

(MAX793/MAX794)

VCE OUT

25µs

10µs

VBATT

VWDO

(MAX793/MAX794)

VBOK

(MAX793)

VPFO

(MAX793/MAX794)

25µs

25µs

25µs

VBATT ON

SHOWN FOR VCC = 3.3V to 0V, VBATT = 3.6V, CE IN = GND, PFI = VCC.

TYPICAL DELAY TIMES REFLECT A 40mV OVERDRIVE

MAX794: VRESET IN = VCC (VRST IN / VRST)

Figure 2. Timing Diagram, VCC Falling

25µs

VBATT

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