LTC692(Rev0) 查看數據表（PDF） - Linear Technology
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LTC692 Datasheet PDF : 16 Pages
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LTC692/LTC693
PI FU CTIO S
VCC: 5V Supply Input. The VCC pin should be bypassed
with a 0.1µF capacitor.
VOUT: Voltage Output for Backed Up Memory. Bypass with
a capacitor of 0.1µF or greater. During normal operation,
VOUT obtains power from VCC through an NMOS power
switch, M1, which can deliver up to 50mA and has a typical
ON resistance of 5Ω. When VCC is lower than VBATT, VOUT
is internally switched to VBATT. If VOUT and VBATT are not
used, connect VOUT to VCC.
VBATT: Backup Battery Input. When VCC falls below VBATT,
auxiliary power connected to VBATT, is delivered to VOUT
through PMOS switch, M2. If backup battery or auxiliary
power is not used, VBATT should be connected to GND.
GND: Ground Pin.
BATT ON: Battery On Logic Output from Comparator C2.
BATT ON goes low when VOUT is internally connected to
VCC. The output typically sinks 35mA and can provide base
drive for an external PNP transistor to increase the output
current above the 50mA rating of VOUT. BATT ON goes
high when VOUT is internally switched to VBATT.
PFI: Power Failure Input. PFI is the noninverting input to
the Power Fail Comparator, C3. The inverting input is
internally connected to a 1.3V reference. The Power Failure
Output remains high when PFI is above 1.3V and goes low
when PFI is below 1.3V. Connect PFI to GND or VOUT when
C3 is not used.
PFO: Power Failure Output from C3. PFO remains high
when PFI is above 1.3V and goes low when PFI is below
1.3V. When VCC is lower than VBATT, C3 is shut down and
PFO is forced low.
RESET: Logic Output for µP Reset Control. Whenever VCC
falls below either the reset voltage threshold (4.40V
typically) or VBATT, RESET goes active low. After VCC
returns to 5V, reset pulse generator forces RESET to
remain active low for a minimum of 140ms. When the
watchdog timer is enabled but not serviced prior to a preset
time-out period, reset pulse generator also forces RESET
to active low for a minimum of 140ms for every preset
time-out period (see Figure 11). The reset active time is
adjustable on the LTC693. An external pushbutton reset
can be used in connection with the RESET output. See
Pushbutton Reset in the Applications Information section.
RESET: RESET is an Active High Logic Ouput. It is the
inverse of RESET.
LOW LINE: Logic Output from Comparator C1. LOW LINE
indicates a low line condition at the VCC input. When VCC
falls below the reset voltage threshold (4.40V typically),
LOW LINE goes low. As soon as VCC rises above the reset
voltage threshold, LOW LINE returns high (see Figure 1).
LOW LINE goes low when VCC drops below VBATT (see
Table 1).
WDI: Watchdog Input. WDI is a three level input. Driving
WDI either high or low for longer than the watchdog time-
out period, forces both RESET and WDO low. Floating WDI
disables the Watchdog Timer. The timer resets itself with
each transition of the Watchdog Input (see Figure 11).
WDO: Watchdog Logic Output. When the watchdog input
remains either high or low for longer than the watchdog
time-out period, WDO goes low. WDO is set high whenever
there is a transition on the WDI pin, or LOW LINE goes low.
The watchdog timer can be disabled by floating WDI (see
Figure 11).
CE IN: Logic Input to the Chip Enable Gating Circuit. CE IN
can be derived from microprocessor's address line and/or
decoder output. See Applications Information Section and
Figure 5 for additional information.
CE OUT: Logic Output on the Chip Enable Gating Circuit.
When VCC is above the reset voltage threshold, CE OUT is a
buffered replica of CE IN. When VCC is below the reset
voltage threshold CE OUT is forced high (see Figure 5).
OSC SEL: Oscillator Selection Input. When OSC SEL is
high or floating, the internal oscillator sets the reset active
time and watchdog time-out period. Forcing OSC SEL low
allows OSC IN to be driven from an external clock signal or
an external capacitor to be connected between OSC IN and
GND.
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