LTC692(Rev0) 查看數據表（PDF） - Linear Technology

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LTC692
(Rev.:Rev0)

Microprocessor Supervisory Circuits

Linear Technology 

LTC692/LTC693

PI FU CTIO S

OSC IN: Oscillator Input. OSC IN can be driven by an

external clock signal or an external capacitor can be

connected between OSC IN and GND when OSC SEL is

forced low. In this configuration the nominal reset active

time and watchdog time-out period are determined by

the number of clocks or set by the formula (see

Applications Information section). When OSC SEL is

high or floating, the internal oscillator is enabled and the

reset active time is fixed at 200ms typical. OSC IN selects

between the 1.6 seconds and 100ms typical watchdog

time-out periods. In both cases the time-out period

immediately after a reset is 1.6 seconds typical.

BLOCK DIAGRA

VBATT

VCC

CE IN

PFI

OSC IN

OSC SEL

WDI

M2

M1

–

C2

+

+

C1

–

1.3V

GND

–

C3

+

OSC

TRANSITION

DETECTOR

CHARGE

PUMP

RESET PULSE

GENERATOR

WATCHDOG

TIMER

VOUT

BATT ON

LOW LINE

CE OUT

PFO

RESET

RESET

WDO

LTC692/3 • BD

7

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