ADP3804JRU-12.5 查看數據表（PDF） - Analog Devices
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ADP3804JRU-12.5 Datasheet PDF : 7 Pages
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ADP3804
Typical values of RCS are in the range from 25 mW to 50 mW,
approximately 200 nsec to ensure that the boost capacitor is
and the input range of ISET is from 0 V to 4 V. If, for example, always charged. This off time sets the maximum duty cycle.
a 2 A charger is required, then RCS could be set to 50 mW and
VISET = 2.5 V. The power dissipation in RCS should be kept
below 500 mW. In this example, the power is a maximum of
200 mW. Once RCS has been chosen, the charge current can be
adjusted during operation with VISET. Lowering VISET to
125 mV gives a charge current of 100 mA for trickle charging.
For example, a 200 kHz frequency (5 µsec period) gives a
maximum duty cycle of 96%.
The oscillator frequency is set by the external capacitor at the
CT pin and the internal current source of 150 µA according to
the following formula:
Components R3, R4, and C13 provide high frequency filtering
for the current sense signal.
fOSC
=
150mA
2 ×CT ×1.5V
(4)
Final Battery Voltage Control
As the battery approaches its final voltage, the ADP3804
switches from CC mode to CV mode. The change is achieved
by the common output node of gm1 and gm2. Only one of the
two outputs controls the voltage at the COMP pin. Both ampli-
fiers can only pull down on COMP, such that when either
amplifier has a positive differential input voltage, its output is
not active. For example, when the battery voltage, VBAT, is low,
A 200 pF capacitor sets the frequency to 250 kHz. The fre-
quency can also be synchronized to an external oscillator by
applying a square wave input on SYNC. The SYNC function is
designed to allow only increases in the oscillator frequency.
The fSYNC should be no more than 20% higher than fOSC. The
duty cycle of the SYNC input is not important and can be
anywhere between 5% and 95%.
gm2 does not control VCOMP. When the battery voltage reaches
7V Boost Regulator
the desired final voltage, gm2 takes control of the loop, and the
charge current is reduced.
Y Amplifier gm2 compares the battery voltage to the internal refer-
R ence voltage of 2.5 V. In the case of the ADP3804-12.5 and
A ADP3804-12.6, an internal resistor divider sets the final battery
IN voltage to 12.6 V. In contrast, the ADP3804 requires external,
L precision resistors. The divider ratio should be set to divide the
IM A desired final voltage down to 2.5 V at the BAT pin:
EL IC R11 = VBATTERY -1
R N R12
2.5V
(2)
P CH These resistors should be high impedance to limit the battery
E A leakage current. Alternatively, an external NMOS can be added
T T in series with R12 to turn off during shutdown. In the case of
DA the ADP3804-12.5 and ADP3804-12.6, an internal MOSFET
The driver stage is powered by the internal 7V boost regulator,
which is available at the BSTREG pin. Because the switching
currents are supplied by this regulator, decoupling must be
added. A 0.1 µF capacitor should be placed close to the
ADP3804, with the ground side connected close to the power
ground pin, PGND. This supply is not recommended for use
externally due to high switching noise.
Boosted Synchronous Driver
The PWM comparator controls the state of the synchronous
driver. A high output from the PWM comparator forces DRVH
on and DRVL off. The drivers have an ON resistance of ap-
proximately 5 W for fast rise and fall times when driving exter-
nal MOSFETs. Furthermore, the boosted drive allows an
external NMOS transistor for the main switch instead of a
PMOS. A boost diode is internally connected between
BSTREG and BST, and a boost capacitor of 0.1 µF must be
disconnects the internal divider to reduce the leakage current
added externally between BST and SW. The voltage between
into BAT to less than 1 µA during shutdown. If the ADP3804- BST and SW is typically 6 V.
12.5 or ADP3804-12.6 is used, then R11 should be shorted
and R12 open. The reference and internal resistor divider are
referenced to the AGND pin, which should be connected close
to the negative terminal of the battery to minimize sensing
errors.
The DRVL pin switches between BSTREG and PGND. The 7
V output of BSTREG drives the external NMOS with high
VGS to lower the ON resistance. PGND should be connected
close to the source pin of the external synchronous NMOS.
When DRVL is high, this turns on the lower NMOS and pulls
Final Battery Voltage Adjust
the SW node to ground. At this point, the boost capacitor is
The ADJ pin provides an analog input to adjust the final bat-
charged up through the internal boost diode. When the PWM
tery voltage by ± 5%. Figure 2 shows the control curve for this switches high, DRVL is turned off and DRVH turns on.
amplifier. Above the threshold voltage of 4.6 V, the amplifier is DRVH switches between BST and SW. When DRVH is on,
turned off. Thus, to disable this function, ADJ should be con- the SW pin is pulled up to the input supply (typically 16 V),
nected to REG. In the linear range between 1 V and 4 V, the
and BST rises above this voltage by approximately 6 V.
percentage change in VBAT is a function VADJ as follows:
Overlap protection is included in the driver to ensure that both
DVBAT
%
=
100 × VADJ
- 2.5V
30
external MOSFETs are not on at the same time. When DRVH
(3)
turns off the upper MOSFET, the SW node goes low due to
the inductor current. The ADP3804 monitors the SW voltage,
This percent change is the same for the ADP3804 (2.5 V out-
put) and the ADP3804-12.6.
Oscillator and PWM
The oscillator generates a triangle waveform between 1 V and
2.5 V, which is compared to the voltage at the COMP pin,
and turns on DRVL when SW goes below 1 V. If, under low
current loads, the SW voltage does not drop below 1 V, DRVL
will turn on after time-out of 200 nsec. When DRVL turns off,
an internal timer adds a delay of 50 nsec before turning DRVH
on.
setting the duty cycle of the driver stage. When VCOMP is below
1 V, the duty cycle is zero. Above 2.5 V, the duty cycle reaches
its maximum. The ADP3804 forces a minimum off time of
–6–
REV. PrI
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