CXD1852Q 查看數據表（PDF） - Sony Semiconductor
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CXD1852Q Datasheet PDF : 30 Pages
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3-5-3. Parallel Mode, Register Read
HA0 to 8
XHCS
(CS)
XHRW
(WR)
XHDT
(WAIT)
HD0 to 7
tWCSH
tSR
tDWA3
tDWA2
tLZQ1
tDQ1
tDQ2
tDQ4
CXD1852Q
tHR
tHZQ1
valid output
Item
Symbol Min. Max. Unit Remarks
Chip disable time
Read setup time
Read hold time
Wait signal delay time (for CE)
Wait signal delay time (for HA)
HD output enable time (for CE)
HD output determination time (for CE)
HD output determination time (for HA)
HD output determination time (for WAIT)
HD output disable time (for CE)
tWCSH
20
tSR
10
tHR
10
tDWA2
—
tDWA3
—
tLZQ1
0
tDQ1
—
tDQ2
0
tDQ4
—
tHZQ1
—
—
ns
—
ns
—
ns
15
ns ∗1
15
ns ∗1
—
ns ∗2
60
ns ∗3
60
ns ∗3
30
ns ∗3, ∗4
15
ns
∗1 Applies only to access resulting in wait status. XHDT goes low at the later timing of CE or HA.
∗2 HD output is enabled when both conditions are met.
∗3 HD output is determined when all conditions are met.
∗4 Applies only to access resulting in wait status.
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