CXD1852Q 查看數據表（PDF） - Sony Semiconductor

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CXD1852Q

MPEG1 Decoder

Sony Semiconductor 

3-5-2. Parallel Mode, Register Write

HA0 to 3

XHCS

tSA

tWCSH

XHRW

XHDT

HD0 to 7

tDWA1

tHZQ2

output

CXD1852Q

tHA

tWWL1

tHW1

tSD1

input

tHD1

Item

Symbol Min.

Address setup time

Address hold time

tSA

20

tHA

20

Chip disable time

Write pulse width

Write pulse hold time

Wait signal delay time

HD output disable time (for WR)

HD input setup time

HD input hold time

tWCSH

20

tWWL1

60

tHW1

10

tDWA1

—

tHZQ2

—

tSD1

25

tHD1

25

∗1 Specified for the edge of XHCS or HRW, whichever is later.

∗2 Specified for the edge of XHCS or HRW, whichever is earlier.

∗3 Interval during which both XHCS and HRW are low.

∗4 Applies only to access resulting in wait status.

∗5 Do not apply data while output is enabled.

Max.

—

—

—

—

—

15

15

—

—

Unit Remarks

ns ∗1

ns ∗2

ns

ns ∗3

ns ∗2, ∗4

ns ∗1, ∗4

ns ∗5

ns ∗2

ns ∗2

–9–

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