VSC8122-FEC 查看數據表（PDF） - Vitesse Semiconductor
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VSC8122-FEC Datasheet PDF : 14 Pages
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Data Sheet
VSC8122-FEC
VITESSE
SEMICONDUCTOR CORPORATION
Multi-Rate SONET/SDH FEC
Clock and Data Recovery IC
Table 2: Reference Frequency
OC-48
19.44MHz
38.88MHz
77.76MHz
155.52MHz
Reference Frequency
OC-48 FEC
20.74MHz(1)
41.47MHz(1)
82.9MHz(1,2)
165.89MHz(1,2)
Gigabit Ethernet
19.53MHz
39.06MHz
78.13MHz
156.25MHz
REF_SEL0
0
1
0
1
REF_SEL1
0
0
1
1
NOTES: (1) Indicates FEC reference clock frequency for use with VSC9210 FEC device running at 2.65Gb/s. (Reference clock
frequencies can operate at frequencies up to 2.66606GHz / Y, where Y = 16, 32, 64, 128.). (2) Indicates recommended
reference clock frequencies.
Loop Filter
The Phase Locked Loop (PLL) on the VSC8122-FEC employs two external capacitors. The PLL design is
fully differential; therefore, the loop filter must also be fully differential. One capacitor should be connected
between FILTAO and FILTAI, with the other connected between FILTAON and FILTAIN. Recommended
capacitors are low inductance 1.0µF (0603 or 0805) ceramic SMT X7R devices, 6.3 WVDC or greater.
AC Characteristics (Over recommended operating conditions)
Table 3: AC Characteristics
Parameter
s
Description
Min
tpd
Center of output data eye from rising
edge of CO+
-75
tr, tf
DO± rise and fall times
—
tr, tf
CO± rise and fall times
—
Max
+75
150
135
Jittergen
Jitter Generation
—
3.6
Jittertol
LBW
Jitterpeak
Jitter Tolerance
Loop Bandwidth
Jitter Peaking
—
—
—
2.0
—
0.1
Units
Conditions
ps
ps.
ps
ps -
rms
—
MHz
dB
20% to 80% into 50Ω load.
20% to 80% into 50Ω load.
Measured at the high-speed
data output for jitter in the
12kHz - 20MHz band.
Assume 1.2ps rms input
data jitter.
Exceeds SONET/SDH
mask
-3dB point of jitter transfer
curve
G52300-0, Rev 4.1
03/01/01
© VITESSE SEMICONDUCTOR CORPORATION • 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
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