VITESSE
SEMICONDUCTOR CORPORATION
Multi-Rate SONET/SDH FEC
Clock and Data Recovery IC
Data Sheet
VSC8122-FEC
Figure 5: High-Speed Clock and Data Outputs
80%
DO
20%
tPD
tr,tf
80%
CO
20%
tr
tf
Table 4: High-Speed Inputs and Outputs
Parameters
Description
Min Typ Max Units
Conditions
∆VOD
∆VOC
VCMO
VDIFF
RIN
Data output voltage swing
600 900 1000 mV
Clock output voltage swing
400 700 1000 mV
Common-mode range (DO/CO)
2.6
—
3.2
V
Serial input absolute voltage, single-ended
peak-to-peak swing (VIH-VIL) for DI +/-
250
Input resistance between DI+ and VTERM or
DI- and VTERM
43
— 1200 mV AC-coupled
—
58
Ω
Table 5: PLL Parameters
Parameters
Description
REF_CLK duty cycle
REF_CLK frequency range
VIH
REF_CLK input HIGH voltage
VIL
REF_CLK input LOW voltage
Min Typ Max Units
45
—
55
%
-100 — +100 ppm
VCC-
—
1.165
VCC-
0.7
V
VCC-
2.0
—
VCC-
1.475
V
Conditions
Page 6
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Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52300-0, Rev 4.1
03/01/01