CS493005 查看數據表（PDF） - Cirrus Logic

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CS493005

Multi-Standard Audio Decoder Family

Cirrus Logic 

CS49300 Family DSP

Table 20. Input SCLK Polarity Configuration

(Input Parameter C) .............................................................................................. 77

Table 21. Input FIFO Setup Configuration

(Input Parameter D) .............................................................................................. 77

Table 22. Output Clock Configuration

(Parameter A) ....................................................................................................... 78

Table 23. Output Data Format Configuration

(Parameter B) ....................................................................................................... 78

Table 24. Output MCLK Configuration

(Parameter C) ....................................................................................................... 79

Table 25. Output SCLK Configuration

(Parameter D) ....................................................................................................... 79

Table 26. Output SCLK Polarity Configuration

(Parameter E) ....................................................................................................... 79

Table 27. Example Values to be Sent to CS493XX After Download or Soft Reset.............. 81

DS339F7

5

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