T8532-JL-DB(2001) 查看數據表（PDF） - Agere -> LSI Corporation
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T8532-JL-DB Datasheet PDF : 50 Pages
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Preliminary Data Sheet
September 2001
T8531A/T8532 Multichannel Programmable
Codec Chip Set
Pin Information (continued)
Table 2. T8531A Pin Descriptions (continued)
Number
23
21
54
51
53, 52
7
4
5
6
48
59
60
61
8
1, 12, 14, 64
55
58
3, 10, 16, 19,
25, 31, 34, 46,
50, 56, 62
2, 9, 15, 18, 26,
32, 33, 41, 47,
49, 57, 63
Name
SDX
SFS
CDO
CDI
CCS[1:0]
TCK
TDI
TDO
TMS
JTESTB
HIGHZB
TEST
CK16
TSTCLK
NC
T_SYNC
RSTB
VDD
VSS
Type
Name/Function
TO Transmit PCM Output. This pin remains in the high-impedance state
except during the transmit time slots as defined in the TSA registers.
Data is shifted out on the rising edge of SCK.
TI Frame Sync. Active-high pulse or square wave with an 8 kHz pulse
repetition rate. The rising edge defines the start of the transmit and
receive frames.
CO T8532 Control Data Output. Control register information for the T8532
chips. Data is valid only when either CCS0 or CCS1 is low.
TIu T8532 Control Data Input. Control register information from the T8532
chips. Data is valid only when either CCS0 or CCS1 is low. An internal
pull-up device is provided.
CO Control Interface Chip Select (Active-Low). These active-low outputs
select one of the associated T8532 chips.
TI JTAG Test Port*-Common Test Clock. Rate ≤20 MHz.
TIu JTAG Test Port*-Serial Data Input. A pull-up device is provided.
TO JTAG Test Port*-Serial Data Output.
TIu JTAG Test Port*-Mode Select. A pull-up device is provided.
TIu JTAG Test. Used for factory testing. Do not make any connection to this
pin. A pull-up device is provided.
TIu 3-State Control Pin (Active-Low). When pulled low, the device output
pins go into a high-impedance state. A pull-up device is provided.
CIu Test Mode Input (Active-Low). This input allows bypass of clock synthe-
sizer and uses TSTCLK to drive the chip. A pull-up device is provided.
CO 16 MHz Clock Output. 16.384 MHz clock output (50% duty cycle). This
clock is present at all times and can be used to drive a host processor.
CI Test Clock.
— No Connect. This pin may be used as a tie point.
CIu Test Sync (Active-Low). Used for factory testing. Do not make any con-
nection to this pin. A pull-up device is provided.
TIu Reset (Active-Low). A logic low initiates reset. A pull-up device is pro-
vided.
— 5 V Digital Power Supply. Power supply decoupling capacitors (0.1 µF)
should be connected from each VDD pin to ground. Capacitors should be
located as close as possible to the device pins.
— Digital Ground.
* The DSP is not configured for boundary scan operation.
Note: TI = TTL input, TO = TTL output; CI = CMOS input, CO = CMOS output; AI = analog input, AO = analog output; Iu indicates that a pull-
up device is included on this lead, Id indicates that a pull-down device is included on this lead.
Agere Systems Inc.
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