T8532-JL-DB(2001) 查看數據表（PDF） - Agere -> LSI Corporation

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T8532-JL-DB
(Rev.:2001)

Multichannel Programmable Codec Chip Set

Agere -> LSI Corporation 

T8531A/T8532 Multichannel Programmable

Codec Chip Set

Preliminary Data Sheet

September 2001

Table of Contents

Contents

Page Contents

Page

Features ..................................................................... 1

General Description.................................................... 1

T8532 Description.................................................... 4

T8531A Description ................................................. 5

Pin Information ........................................................... 7

Chip Set Functional Description ............................... 12

Transmit Path......................................................... 12

Antialias Filter and Σ-∆ Converter ...................... 12

Decimator ........................................................... 12

Digital Transmit Gain Adjustment........................ 12

Band Filtering ...................................................... 12

µ-Law, A-Law, and Linear PCM Modes............... 12

Receive Path ......................................................... 13

Receive Path Filtering ......................................... 13

Digital Receive Gain............................................ 13

Interpolator and Digital Sigma-Delta

Modulator.......................................................... 13

Decoder, Filters, and Receive Amplifier ............. 13

Other Chip Set Functions....................................... 13

Voltage Reference............................................... 13

Hybrid Balance .................................................... 13

Analog Termination Impedance Synthesis.......... 13

Digital Termination Impedance Synthesis ........... 14

Loopback Modes ................................................. 14

Interchip Control Interface ................................... 14

T8531A Functional Blocks ..................................... 14

Clock Synthesizer................................................ 14

T8531A System Interface ................................... 15

T8531A Microprocessor Interface ....................... 15

T8532 Octal Control Interface ............................. 16

T8531A Time-Slot Assignment (TSA) ................. 16

DSP Engine Timing................................................ 16

T8531A Program Structure ................................. 16

Control of the DSP Engine via the

Microprocessor Interface .................................. 17

The DSP Engine Time-Slot Information

Tables ............................................................... 17

The DSP Engine ac Path Coefficient Table ........ 17

The Time-Slot Control Word................................ 18

Operations Performed by the DSP Engine at

T8531A Start-Up............................................... 18

Microprocessor Start-Up of the DSP Engine....... 19

Powering Up a Time Slot in the T8531................ 19

Disabling a Time Slot in the T8531 ..................... 19

T8532 Powerup/Powerdown ............................... 19

Changing DSP RAM Space of an Active

Time Slot........................................................... 20

DSP Engine Memory Requirements ................... 20

T8531A Reset and Start-Up................................... 20

Hardware Reset .................................................. 20

Internal Reset ...................................................... 21

Reset of the T8532 Devices ................................ 21

Start-Up After Internal Reset.................................. 21

Autocalibration..................................................... 22

User Test Features ................................................ 22

Off-Line Programmable System Test

Capability .......................................................... 22

On-Line Per-Channel Test Capability.................. 22

Inactive Mode with Loopback .............................. 22

Self-Test and Line-Test Routines .......................... 22

Tone Generation ................................................. 22

Tone Detection .................................................... 23

dc Generation...................................................... 23

dc Measurement.................................................. 23

Variance Computation......................................... 23

Peak Detection .................................................... 23

Tone Plant.............................................................. 23

DTMF Transceiver............................................... 23

Caller Line Identification ...................................... 23

Call Progress Tones............................................ 23

Absolute Maximum Ratings...................................... 24

Handling Precautions ............................................... 24

Electrical Characteristics .......................................... 25

dc Characteristics .................................................. 25

Transmission Characteristics ................................... 26

Timing Characteristics .............................................. 30

Software Interface .................................................... 33

Applications .............................................................. 44

Common Voltage Reference.................................. 47

Outline Diagrams...................................................... 48

64-Pin MQFP ......................................................... 48

64-Pin TQFP .......................................................... 49

Ordering Information................................................. 50

Appendix A. Transmit Path Group Delay vs. Bit

Offset ................................................................ 50

2

Agere Systems Inc.

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