DS1991 查看數據表（PDF） - Dallas Semiconductor -> Maxim Integrated

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DS1991

MultiKey iButton™

Dallas Semiconductor -> Maxim Integrated 

DS1991

INITIALIZATION PROCEDURE “RESET AND PRESENCE PULSES” Figure 10

RESISTOR

MASTER

DS1991

480 µs ≤ tRSTL < ∞ *

480 µs ≤ tRSTH < ∞(includes recovery time)

15 µs ≤ tPDH < 60 µs

60 µs ≤ tPDL < 240 µs

∗ In order not to mask interrupt signaling by other devices on the 1-Wire bus, tRSTL + tR should always

be less than 960 µs.

READ/WRITE TIME SLOTS

The definitions of write and read time slots are illustrated in Figure 11. All time slots are initiated by the

master driving the data line low. The falling edge of the data line synchronizes the DS1991 to the master

by triggering a delay circuit in the DS1991. During write time slots, the delay circuit determines when the

DS1991 will sample the data line. For a read data time slot, if a “0” is to be transmitted, the delay circuit

determines how long the DS1991 will hold the data line low overriding the 1 generated by the master. If

the data bit is a “1”, the iButton will leave the read data time slot unchanged.

READ/WRITE TIMING DIAGRAM Figure 11

Write-One Time Slot

RESISTOR

MASTER

60 µs ≤ tSLOT < 120 µs

1 µs ≤ tLOW1 < 15 µs

1 µs ≤ tREC < ∞

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