UPA1760 查看數據表（PDF） - NEC => Renesas Technology
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UPA1760 Datasheet PDF : 8 Pages
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µPA1760
ELECTRICAL CHARACTERISTICS (TA = 25°C, All terminals are connected.)
CHARACTERISTICS
SYMBOL
TEST CONDITIONS
MIN. TYP. MAX. UNIT
Drain to Source On-state Resistance
RDS(on)1 VGS = 10 V, ID = 4.0 A
20.5 26.0 mΩ
RDS(on)2 VGS = 4.5 V, ID = 4.0 A
27.0 36.0 mΩ
RDS(on)3 VGS = 4.0 V, ID = 4.0 A
31.0 42.0 mΩ
Gate to Source Cut-off Voltage
VGS(off) VDS = 10 V, ID = 1 mA
1.5 2.1 2.5 V
Forward Transfer Admittance
| yfs | VDS = 10 V, ID = 4.0 A
3.0 7.5
S
Drain Leakage Current
IDSS
VDS = 30 V, VGS = 0 V
10 µA
Gate to Source Leakage Current
IGSS
VGS = ±16 V, VDS = 0 V
±10 µA
Input Capacitance
Ciss
VDS = 10 V
760
pF
Output Capacitance
Coss
VGS = 0 V
250
pF
Reverse Transfer Capacitance
Crss
f = 1 MHz
95
pF
Turn-on Delay Time
td(on)
ID = 4.0 A
20
ns
Rise Time
tr
VGS(on) = 10 V
140
ns
Turn-off Delay Time
td(off)
VDD = 15 V
50
ns
Fall Time
tf
RG = 10 Ω
30
ns
Total Gate Charge
QG
ID = 8.0 A
14
nC
Gate to Source Charge
QGS
VDD = 24 V
2.0
nC
Gate to Drain Charge
QGD
VGS = 10 V
5.0
nC
Body Diode Forward Voltage
VF(S-D) IF = 8.0 A, VGS = 0 V
0.86
V
Reverse Recovery Time
trr
IF = 8.0 A, VGS = 0 V
30
ns
Reverse Recovery Charge
Qrr
di/dt = 100A/µs
20
nC
TEST CIRCUIT 1 AVALANCHE CAPABILITY
D.U.T.
RG = 25 Ω
L
PG.
50 Ω
VDD
VGS = 20 → 0 V
IAS
ID
VDD
BVDSS
VDS
Starting Tch
TEST CIRCUIT 3 GATE CHARGE
D.U.T.
IG = 2 mA
RL
PG.
50 Ω
VDD
TEST CIRCUIT 2 SWITCHING TIME
D.U.T.
PG.
RG
RG = 10 Ω
VGS
0
τ
τ = 1 µs
Duty Cycle ≤ 1 %
RL
VDD
VGS
VGS
Wave Form
10 %
0
ID
ID
Wave Form
0 10 %
VGS(on)
90 %
ID
90 %
90 %
10 %
td(on)
tr td(off)
tf
ton
toff
2
Data Sheet G13891EJ2V0DS
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