NDS351N 查看數據表（PDF） - Fairchild Semiconductor
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NDS351N Datasheet PDF : 6 Pages
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March 1996
NDS351N
N-Channel Logic Level Enhancement Mode Field Effect Transistor
General Description
These N-Channel logic level enhancement mode power
field effect transistors are produced using Fairchild's
proprietary, high cell density, DMOS technology. This
very high density process is especially tailored to
minimize on-state resistance. These devices are
particularly suited for low voltage applications in notebook
computers, portable phones, PCMCIA cards, and other
battery powered circuits where fast switching, and low
in-line power loss are needed in a very small outline
surface mount package.
Features
1.1A, 30V. RDS(ON) = 0.25Ω @ VGS = 4.5V.
Proprietary package design using copper lead frame for
superior thermal and electrical capabilities.
High density cell design for extremely low RDS(ON).
Exceptional on-resistance and maximum DC current
capability.
Compact industry standard SOT-23 surface mount
package.
________________________________________________________________________________
D
G
S
Absolute Maximum Ratings
Symbol Parameter
TA = 25°C unless otherwise noted
VDSS
Drain-Source Voltage
VGSS
Gate-Source Voltage - Continuous
ID
Maximum Drain Current - Continuous
- Pulsed
PD
Maximum Power Dissipation
(Note 1a)
(Note 1a)
(Note 1b)
TJ,TSTG Operating and Storage Temperature Range
THERMAL CHARACTERISTICS
RθJA
RθJC
Thermal Resistance, Junction-to-Ambient
Thermal Resistance, Junction-to-Case
(Note 1a)
(Note 1)
NDS351N
30
20
± 1.1
± 10
0.5
0.46
-55 to 150
250
75
© 1997 Fairchild Semiconductor Corporation
Units
V
V
A
W
°C
°C/W
°C/W
NDS351N Rev. E2
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