SSM1105 查看數據表（PDF） - STMicroelectronics

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SSM1105

Scalar System Memory (SSM) for Image Processor ICs

STMicroelectronics 

SSM1105V

SUMMARY DESCRIPTION

SSM1105V devices bring in-system programma-

ble (ISP) and in-application programmable (IAP)

flash memory to LCD monitor, projector and televi-

sion applications utilizing a scalar IC from either

Pixelworks or other similar image processors or

micro-controllers (MCU). Figure 3 shows a typical

SSM based system with Pixelworks processor.

The SSM1105V devices feature a dual -bank flash

architecture, Dual Display Data Channels (DDC),

I2C, PWM channels, general purpose I/O, pro-

grammable logic, and in-system programming via

either JTAG or I2C.

Figure 2. SSM Block Diagram

The dual-bank Flash memory architecture sup-

ports full concurrent operation permitting IAP in

the field, which means that firmware can be re-

motely updated with little interruption of system

operation. During run-time, the secondary Flash

memory array is ideal for EEPROM emulation,

thus eliminating the need for a separate external

EEPROM.

An on-chip, decode PLD provides for flexible ad-

dress mapping for both memories. Dual 256 byte

SRAMs provide buffer storage for the DDC chan-

nels, thus removing the burden from the proces-

sor.

CPU ADDR

AD0

AD1

AD2

AD3

AD4

AD5

AD6

AD7

AD8

AD9

AD10

AD11

AD12

AD13

AD14

AD15

CPU DATA

PF0

PF1

PF2

PF3

PF4

PF5

PF6

PF7

PG0

PG1

PG2

PG3

PG4

PG5

PG6

PG7

CPU CNTL

CNTL0

CNTL1

CNTL2

RST\

INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU

SECURITY

LOCK

PAGE REG

MAIN FLASH

10 BLOCKS, 64 KB

640 KBytes total

DECODE

PLD

FS0-9

CSBOOT0-5

SECONDARY FLASH

6 BLOCKS, 8 KB

48 KBytes total

DDC-SRAM

DDC SRAMs

256 byte 256 byte

CSIP

CSIOP

RUNTIME CONTROL

REG FILES

DDC

I2C

PWM

GPIO

POWER MNGMT

GENERAL PLD

AND

ARRAY

A AA A A AA A

B BBB B BBB

16 OUTPUT MICROCELLS

AAA AAAAACCCC

BBB BBBBBCCCC

24 INPUT

MICROCELLS

PIN FEEDBACK

NODE FEEDBACK

DUAL I2C

I2C0

I2C1

INTERNAL ADDR, DATA, CONTROL BUS LINKED TO CPU

JTAG ISP

CONTROLLER

DUAL DDC

DDC0

DDC1

QUAD PWM

PW0 PW1 PW2 PW3

TO PLD

IN BUS

I/O PORT

P PP P PPPP

E EE E EEEE

0 12 3 4567

I/O PORT

P PP P P PPP

H HH H H HHH

0 12 3 4 567

I/O PORT

PPPP PPPP

IIII IIII

0123 4567

I/O PORT

PD0

PD1

PD2

PD3

I/O PORT

PA0

PA1

PA2

PA3

PA4

PA5

PA6

PA7

I/O PORT

PB0

PB1

PB2

PB3

PB4

PB5

PB6

PB7

I/O PORT

PC0

PC1

PC2

PC3

PC4

PC5

PC6

PC7

AI04976

Note: Additional address lines can be brought in to the device via Port A, B, C or D.

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