VSC6501 查看數據表（PDF） - Vitesse Semiconductor

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VSC6501

and Cable Driver at 1.485 Gb/s SMPTE-292M Reclocker

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

SMPTE-292M Reclocker and

Cable Driver at 1.485 Gb/s

Advance Product Information

VSC6501

Reclocker Functional Description

Clock Multiplier Unit (CMU)

The CMU generates the internal 1.485 GHz baud rate clock from the 74.25 MHz TTL REFCLK input. The

rising edges of the REFCLK are used by a PLL which multiplies the frequency by a factor of 20. An off-chip

0.1uF capacitor sets the loop bandwidth of the CMU. REFCLK should be a high quality, low jitter signal with

sharp rise times in order to minimize the amount of jitter transferred from the REFCLK through the CMU to the

serializer. Although not shown on the block diagram, the digital CRU requires the baud rate clock of the CMU

for proper operation.

REFCLK is also buffered onto the RCLK output allowing multiple devices to be daisy-chained in order to

simplify REFCLK distribution to an array of devices.

Serial Input

The differential PECL-style input, SDI/SDI, is the input source for 1.485 Gb/s SMPTE 292M data. An ana-

log signal detector monitors the input signal for valid amplitude and outputs status on the SIGDET pin. If SIG-

DET is HIGH, the differential input swing is greater than 400 mV. If SIGDET is LOW, the differential swing is

below 200 mV. If the input swing is between 200 and 400 mV, the SIGDET output is indeterminate. The SIG-

DET function is disabled in Serializer mode and will output a LOW.

Clock Recovery Unit

The serial data on the SDI/SDI input is sent to the digital Clock Recovery Unit (CRU) which extracts the

clock and retimes the data. This digital CRU is completely monolithic and requires no external components.

Furthermore, it automatically locks onto data when present and locks to REFCLK when data is not present. This

eliminates the need for the system to control the CRU.

Descrambler and NRZI Decoder

The VSC6501 contains a descrambler which processes the recovered serial data and outputs unscrambled

serial data from the deserializer. The serial scrambled data is descrambled/NRZI decoded assuming data has

NRZI encoded with the following combined generator polynomial: G(x)=(x9+x4+1)(x+1). Descrambling is

enabled with the SCREN input is HIGH and disabled when LOW.

Pattern Detector

The VSC6501 monitors the serial data stream for SAV/EAV characters. These characters should be located

within each line of video data. If SAV/EAV is not detected within the period of one line, the Framer sends a sig-

nal to the Deserializer to shift the data one bit. The Frame then looks for SAV/EAV and the process repeats until

properly detected. Without these patterns, serial data is not aligned in any way with the parallel outputs. The

Framer outputs a once-per-line (LINE) and a once-per-frame (FRAME) signal indicating the detection of the

proper synchronization pulse in the data.

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© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52310-0, Rev. 2.0

4/10/00

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