VSC6501 查看數據表（PDF） - Vitesse Semiconductor

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VSC6501

and Cable Driver at 1.485 Gb/s SMPTE-292M Reclocker

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC6501

SMPTE-292M Reclocker

and Cable Driver at 1.485 Gb/s

The output swing of the VSC6501 is controlled through the ISETx pins and a VREF input. By connecting

an 1.78K ohm resistor, 1%, between VSS and ISETx the output swing will be controlled to within 800mV +/-

7%. An optional bandpass voltage reference may be used to further tighten the output swings by accurately driv-

ing the VREF input.

Figure 3: REFCLK Timing Waveforms

REFCLK

TL

TH

TR

VIH(MIN)

VIL(MAX)

Table 3: Reference Clock Requirements *

Parameters

Description

FR

Frequency Range

FO

Frequency Offset

DC

REFCLK duty cycle

TH, TL

REFCLK high/low times

TR

REFCLK rise

Note: The PLL locks to the rising edge of REFCLK.

Min

73.75

-1000

-15

3.0

—

Max

74.50

1000

+15

—

2.0

Units

MHz

ppm.

%

ns.

ns.

Conditions

Will accept both 74.176/74.25MHz

Difference in REFCLK frequencies

between the transmitting and receiving

VSC6501s.

Measured at 1.5V

Measured between VIL(MAX) to VIL(MAX)

or VIH(MIN) to VIH(MIN)

Between VIL(MAX) and VIH(MIN)

Figure 4: RCLK Timing Waveforms*

RCLK

TL

TH

TR

VIH(MIN)

VIL(MAX)

G52310-0, Rev. 2.0

4/10/00

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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