VSC9142 查看數據表（PDF） - Vitesse Semiconductor

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VSC9142

STS-48c Packet/ATM Over SONET/SDH Device With Integrated Mux/Demux and Clock and Data Recovery

Vitesse Semiconductor 

VITESSE

SEMICONDUCTOR CORPORATION

Preliminary Datasheet

VSC9142

STS-48c Packet/ATM Over SONET/SDH Device

With Integrated Mux/Demux and Clock and Data Recovery

Symbol

Tr/f, RLCLK4

Tjitter, RLCLK4

Tsu, RLIN4

Th, RLIN4

Description

RLCLK4+/- rise/fall time (20-80%)

RLCLK4+/- cycle-to-cycle

RLIN4[3..0]+/-, RLPRTY4+/- setup time to RLCLK4+ rising

edge

RLIN4[3..0]+/-, RLPRTY4+/- hold time to RLCLK4+ rising

edge

Min

-

+300

+300

Figure 3: Tx Parallel Line Interface Timing Dependencies

Max

200

100

-

-

Unit

ps

ps

ps

ps

TLCLKOUT4+

TLOUT4[3..0]+/-

TLPRTY4+/-

TP,TLOUT

TLCLK4+

TLSYNCLVDS+/-

TLSYNCTTL

TSU,TLSYNC

TH,TLSYNC

TPW,TLSYNC

Table 3: Tx Parallel Line Interface

Symbol

fTLCLKOUT4

Tdc, TLCLKOUT4

Tr/f, TLCLKOUT4

Tp, TLOUT

fTLCLK4

Tdc, TLCLK4

Tr/f, TLCLK4

Tjitter, TLCLK4

Tsu, TLSYNC

Description

TLCLKOUT4+/- clock frequency (nominal)

TLCLKOUT4+/- duty cycle

TLCLKOUT4+/- rise/fall time (20-80%)

TLCLKOUT4+ rising edge to TLOUT4[3..0]+/-, TLPRTY4+/-

valid

TLCLK4+/- clock frequency (nominal)

TLCLK4+/- duty cycle

TLCLK4+/- rise/fall time (20-80%)

TLCLK4+/- cycle-to-cycle jitter

TLSYNC setup time to TLCLK4+ rising edge1)

Min

-

40

-

-200

-

45

-

300

Max

622.08

60

200

+200

622.08

55

200

100

-

Unit

MHz

%

ps

ps

MHz

%

ps

ps

ps

G52319-0, Rev. 3.1

6/12/00

 VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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