VSC9111 查看數據表（PDF） - Vitesse Semiconductor

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产品描述 (功能)

生产厂家

VSC9111

SONET/SDH 2.5Gb/s Transport Terminating Transceiver

Vitesse Semiconductor 

Target Specification

VSC9111

VITESSE

SEMICONDUCTOR CORPORATION

SONET/SDH 2.5Gb/s

Transport Terminating Transceiver

CPU and Test Interface:

· Generic microprocessor (CPU) interface used for device configuration, status and performance informa-

tion extraction and test mode operations

· Provides optional hardware generated “ticks” for performance monitoring counter latching

· 8 bit data bus and 8 bit address bus

· Interrupt pin

· General Purpose IOs

· Standard 5 pin JTAG Test Access Port

Drop Interface:

· 32 bit databus which can be configured as one 32 bit bus for STS-48c operation, four 8 bit busses for STS-

12 interfacing, or sixteen 2 bit busses for STS-3 interfacing.

· 77.76MHz operation

· Provides parity bits for receive and transmit interfaces

· Provides separate clock inputs for each STS-3/STS-12 transmit interface to allow point-to-point connec-

tions for improved signal integrity and system robustness

· Features phase synchronizing FIFOs on transmit interfaces to allow flexible system level clocking strate-

gies

Other Features:

· Section loopback mode. Provides termination and regeneration of section overhead. Regenerator applia-

tions

· Line loopback mode. Provides termination and regeneration of section and line overhead. Regenerator

applications where line DCC needs to be accessed/inserted.

· Facility loopback mode. For diagnostics/bypass.

· Equipment loopback mode. For diagnostics/bypass.

· Flexible error insertion capabilities. For diagnostics/tester applications

· Bit Error Rate Monitor with four independent BER threshold levels. Signal Degrade and Signal Fail alarm

status detection.

G52199-0, Rev. 1.2

3/8/99

© VITESSE SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

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