NT68P81 查看數據表（PDF） - Novatek Microelectronics

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NT68P81

USB Keyboard Micro-Controller

Novatek Microelectronics 

NT68P81

11. Watch-Dog Timer (WDT)

The NT68P81 has a watch-dog timer reset function that protects programs against system standstill. The clock of the

WDT is derived from the crystal oscillator. The WDT interval is about 0.15 seconds when the operation frequency is 6MHz.

The timer must be cleared every 0.15 second during normal operation; otherwise, it will overflow and cause a system

reset (This cannot be disabled by the software). Before watch-dog reset occurs, the software will clear the watch-dog

register by writing #55H to CLRWDT ($000EH) register.

For example:

LDA #$55H

STA $000E

12. Power Control

The power-off flag (POF) in the MODE_FG register indicates whether a reset is a warm start or a cold start reset. POF is

set by hardware when an external power VCC arises to its normal operating level, and must be cleared by the software in

the cold reset initialization procedure. A warm start reset (POF = 0) occurs at a watch-dog reset or resume reset.

Address Register Reset

$000FH MODE_FG 02H

Bit 7

-

Bit 6

-

Bit 5

-

Bit 4

-

Bit 3

-

Bit 2

-

Bit 1

POF

Bit 0 R/W

SUSF R/W

13. Universal Serial Bus Interface

Please refer to the UNIVERSAL SERIAL BUS specification Version 1.0 Chapter 7, 8, and 9.

14. Suspend and Resume

Suspend:

When SIE receives the suspend signal, NT68P81 generates a SUSP interrupt request. In the SUSP interrupt service

routine, the software will carry out the following steps:

1) Clear SUSP IRQ flag,

2) Store all the port status,

3) Force return lines (PORT2) pull-high,

4) Force scan lines (PORT0, PORT1 and P30, P31 or P32) pull-low,

5) Turn off LED output,

6) Clear watch-dog register

After the above action has been completed, the software will then set SUSLO ($1EH) to #55H and SUSHI ($1FH) to #AAH

in order to enter the SUSPEND mode. The oscillator will stop for in order to save power.

Resume:

When the SIE detects a resume signal, the NT68P81 trigger oscillator to oscillate and resets whole chip. After a reset,

software checks the status of POF bit in MODE_FG register to see whether a cold start reset or a warm start reset

occurred. If cold reset, it executes all initial procedure. If warm reset, software checks the status of SUSF bit in MODE_FG

register to see whether a watch-dog reset or resume reset. Under resume reset condition, programmer should restores

all port status. After a warm start, user software should clear the SUSF bit. When any key stroked in suspend mode, it

remotely resume NT68P81 functions. The action is same as host resume.

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