ML4805 查看數據表（PDF） - Fairchild Semiconductor

零件编号

产品描述 (功能)

生产厂家

ML4805

Variable Feedforward PFC/PWM Controller Combo

Fairchild Semiconductor 

ML4805

FUNCTIONAL DESCRIPTION (Continued)

Generating VCC

The ML4805 is a voltage-fed part. It requires an external

15V±10% or better Zener shunt voltage regulator, or some

other controlled supply, to regulate the voltage supplied

to the part at 15V nominal. This allows a low power

dissipation while at the same time delivering 13V

nominal of gate drive at the PWM OUT and PFC OUT

outputs. If using a Zener diode, it is important to limit the

current through the Zener to avoid overheating or

destroying it. This can be easily done with a single resistor

in series with the Vcc pin, returned to a bias supply of

typically 18V to 20V. The resistor’s value must be chosen

to meet the operating current requirement of the ML4805

itself (8.5mA max.) plus the current required by the two

gate driver outputs.

EXAMPLE:

With a VBIAS of 20V, a VCC limit of 16.5V (max) and

driving a total gate charge of 110nC at 100kHz (1 IRF840

MOSFET and 2 IRF830 MOSFETs), the gate driver current

required is:

IGATEDRIVE = 100kHz ´ 110nC = 11mA

RBIAS

=

20V - 16.5V

7.5mA + 11mA

= 180Ω

The ML4805 should be locally bypassed with a 10nF and

a 1µF ceramic capacitor. In most applications, an

electrolytic capacitor of between 100µF and 330µF is also

required across the part, both for filtering and as part of

the start-up bootstrap circuitry.

LEADING/TRAILING MODULATION

Conventional Pulse Width Modulation (PWM) techniques

employ trailing edge modulation in which the switch will

turn on right after the trailing edge of the system clock.

The error amplifier output voltage is then compared with

the modulating ramp. When the modulating ramp reaches

the level of the error amplifier output voltage, the switch

will be turned OFF. When the switch is ON, the inductor

current will ramp up. The effective duty cycle of the

trailing edge modulation is determined during the ON

time of the switch. Figure 3 shows a typical trailing edge

control scheme.

In the case of leading edge modulation, the switch is

turned OFF right at the leading edge of the system clock.

When the modulating ramp reaches the level of the error

amplifier output voltage, the switch will be turned ON.

The effective duty-cycle of the leading edge modulation

is determined during the OFF time of the switch. Figure 4

shows a leading edge control scheme.

One of the advantages of this control technique is that it

requires only one system clock. Switch 1 (SW1) turns off

and switch 2 (SW2) turns on at the same instant to

minimize the momentary “no-load” period, thus lowering

ripple voltage generated by the switching action. With

such synchronized switching, the ripple voltage of the

first stage is reduced. Calculation and evaluation have

shown that the 120Hz component of the PFC’s output

ripple voltage can be reduced by as much as 30% using

this method.

L1

I1

+

VIN

DC

SW2 I2 I3

SW1

I4

RL

C1

REF +–EAU3

RAMP

OSC

CLK

+

– U1

U4

DFF

RQ

D U2

Q

CLK

RAMP

VEAO

VSW1

TIME

TIME

Figure 3. Typical Trailing Edge Control Scheme

10

L1 SW2 I2

I3

I1

+

I4

VIN

DC

SW1

RL

C1

+–EAU3

REF

RAMP

OSC

CLK

VEAO

+ CMP

– U1

U4

DFF

RQ

D U2

Q

CLK

RAMP

VEAO

VSW1

TIME

TIME

Figure 4. Leading/Trailing Edge Control Scheme

REV. 1.1 3/9/2001

Share Link: