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August 1998
Table 14: Serial Interface Timing Specifications
Unless otherwise stated, VDD = 5.0V ± 10%, no load on any output, and ambient temperature range TA = 0°C to 70°C. Parameters denoted with an asterisk ( * ) represent nominal characterization
data and are not production tested to any specific limits. MIN and MAX characterization data are ± 3σ from typical.
PARAMETER
SYMBOL
CONDITIONS/DESCRIPTION
STANDARD MODE
MIN.
MAX.
UNITS
Clock frequency
Bus free time between STOP and START
Set up time, START (repeated)
Hold time, START
Set up time, data input
Hold time, data input
Output data valid from clock
Rise time, data and clock
Fall time, data and clock
High time, clock
Low time, clock
Set up time, STOP
fSCL
tBUF
tsu:STA
thd:STA
tsu:DAT
thd:DAT
tAA
tR
tF
tHI
tLO
tsu:STO
SCL
SDA
SDA
Minimum delay to bridge undefined
region of the fall-ing edge of SCL to
avoid unintended START or STOP
SDA, SCL
SDA, SCL
SCL
SCL
0
100
kHz
4.7
µs
4.7
µs
4.0
µs
250
ns
0
µs
3.5
µs
1000
ns
300
ns
4.0
µs
4.7
µs
4.0
µs
Figure 8: Bus Timing Data
SCL
SDA
tsu:STA
thd:STA
START
ADDRESS OR
DATA VALID
DATA CAN
CHANGE
Figure 9: Data Transfer Sequence
SCL
tF
tLO
tsu:STA
thd:STA
SDA
IN
tAA
SDA
OUT
tHI
thd:DAT
tAA
tsu:DAT
tsu:STO
STOP
tR
tsu:STO
tBUF
,62
14
8.19.98