FDC37N958FR 查看數據表（PDF） - SMSC -> Microchip

零件编号

产品描述 (功能)

生产厂家

FDC37N958FR

Notebook I/O Controller with Enhanced Keyboard and System Control

SMSC -> Microchip 

AUTO POWER MANAGEMENT

Auto Power Management (APM) capabilities are

provided for the following logical devices: Floppy

Disk, UART 1, UART 2 and the Parallel Port. For

each logical device, two types of power

management are provided; direct powerdown and

auto powerdown.

System Power Management

See the “8051 System Power Management”

section for details.

FDC Power Management

Disabling the auto powerdown mode cancels the

timer and holds the FDC block out of auto

powerdown.

DSR From Powerdown

Bit 6 of the FDC’s DSR register is another FDC

powerdown bit. If DSR powerdown is used when

the FDC37N958FR is in auto powerdown, the

DSR powerdown will override the auto

powerdown. However, when the FDC37N958FR

is awakened from DSR powerdown, the auto

powerdown will once again become effective.

Direct power management is controlled through

Global Configuration Register 22 (CR22). Refer

to CR22 in the Configuration section for more

information.

Auto Power Management is enabled through bit-0

of CR23. When set, this bit allows the FDC to

enter powerdown when all of the following

conditions have been met:

1. The motor enable pins of the FDC’s DOR

register are inactive (zero).

2. The FDC37N958FR must be idle; the MSR

register = 80h and the FDC’s INTerrupt = 0

(INT may be high even if MSR = 80H due to

polling interrupts).

3. The head unload timer must have expired.

4. The Auto powerdown timer (10msec) must

have timed out.

An internal timer is initiated as soon as the auto

powerdown command is enabled. The

FDC37N958FR is then powered down when all

the conditions are met.

Wake Up From Auto Powerdown

If the FDC37N958FR enters the powerdown state

through the auto powerdown mode, then the

FDC37N958FR can be awakened by reset or by

appropriate access to certain registers.

If a hardware or software reset is used then the

FDC37N958FR will go through the normal reset

sequence. If the access is through the selected

registers, then the FDC resumes operation as

though it was never in powerdown. Besides

activating the RESET pin or one of the software

reset bits in the DOR or DSR registers, the

following register accesses will wake up the

FDC37N958FR:

1. Enabling any one of the motor enable bits in

the DOR register (reading the DOR does not

awaken the FDC37N958FR).

2. A read from the MSR register.

3. A read or write to the Data register.

Once awake, the FDC will reinitiate the auto

powerdown timer for 10 ms.

The

FDC37N958FR will powerdown again when all

the powerdown conditions are satisfied.

SMSC DS – FDC37N958FR

Page 17

Rev. 09/01/99

Share Link: