FDC37N958FR 查看數據表（PDF） - SMSC -> Microchip
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FDC37N958FR Datasheet PDF : 316 Pages
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STATUS REGISTER A (SRA)
FDC I/O Base Address + 0x00 (READ ONLY)
This register is read-only and monitors the state of
the FDC Interrupt pin and several disk interface
pins in PS/2 and Model 30 modes. The SRA can
be accessed at any time when in PS/2 mode. In
the PC/AT mode the data bus pins D0 - D7 are
held in a high impedance state for a read of SRA.
SRA - PS/2 Mode
7
6
5
4
3
2
1
0
INT
nDRV2 STEP nTRK0 HDSEL nINDX nWP DIR
PENDING
RESET
0
N/A
0
N/A
0
N/A N/A
0
COND.
BIT 0 DIRECTION
Active high status indicating the direction of head
movement. A logic "1" indicates inward direction;
a logic "0" indicates outward direction.
BIT 1 nWRITE PROTECT
Active low status of the WRITE PROTECT disk
interface input. A logic "0" indicates that the disk
is write protected.
BIT 2 nINDEX
Active low status of the INDEX disk interface
input.
BIT 3 HEAD SELECT
Active high status of the HDSEL disk interface
input. A logic "1" selects side 1 and a logic "0"
selects side 0.
BIT 4 nTRACK 0
Active low status of the TRK0 disk interface input.
BIT 5 STEP
Active high status of the STEP output disk
interface output pin.
BIT 6 nDRV2
Active low status of the DRV2 disk interface input
pin, indicating that a second drive has been
installed.
BIT 7 INTERRUPT PENDING
Active high bit indicating the state of the Floppy
Disk Interrupt output.
SMSC DS – FDC37N958FR
Page 24
Rev. 09/01/99
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