FDC37N958FR 查看數據表（PDF） - SMSC -> Microchip

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FDC37N958FR

Notebook I/O Controller with Enhanced Keyboard and System Control

SMSC -> Microchip 

Register Behavior

Table 4 shows the AT and PS/2 (including Model

30) configuration registers available. It also shows

the type of access permitted. In order to maintain

software transparency, access to all the registers

is maintained. As Table 4 shows, two sets of

registers are distinguished based on whether their

access results in the FDC37N958FR remaining in

powerdown state or exiting it.

Access to all other registers is possible without

awakening the FDC37N958FR. These registers

can be accessed during powerdown without

changing the status of the FDC37N958FR. A

read from these registers will reflect the true

status as shown in the register description in the

FDC section. Writes to these registers will result

in the FDC37N958FR retaining the data and

subsequently reflecting it when the

FDC37N958FR awakens. Accessing the

FDC37N958FR during powerdown may cause an

increase in the power consumption by the

FDC37N958FR. The FDC37N958FR will revert

back to its low power mode when the access has

been completed.

Pin Behavior

The FDC37N958FR is specifically designed for

portable PC systems in which power conservation

is a primary concern. This makes the behavior of

the pins during powerdown very important.

The pins which interface to the floppy disk drive

are disabled so that no power will be drawn

through the FDC37N958FR as a result of any

voltage applied to the pin within the VCC2 power

supply range. Most of the pins which interface to

the system are left active to monitor system

accesses that may wake up the FDC37N958FR.

SMSC DS – FDC37N958FR

Page 18

Rev. 09/01/99

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