MAX3681(1996) 查看數據表（PDF） - Maxim Integrated
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MAX3681 Datasheet PDF : 8 Pages
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+3.3V, 622Mbps, SDH/SONET
1:4 Deserializer with LVDS Outputs
Low-Voltage Differential-Signal (LVDS)
Inputs and Outputs
The MAX3681 features LVDS inputs and outputs for
interfacing with high-speed digital circuitry. The LVDS
standard is based on the IEEE 1596.3 LVDS specifica-
tion. This technology uses 250mVp-p to 400mVp-p, dif-
ferential low-voltage swings to achieve fast transition
times, minimized power dissipation, and noise immunity.
The parallel clock and data LVDS outputs (PCLK+,
PCLK-, PD_+, PD_-) require 100Ω differential DC termi-
nation between the inverting and noninverting outputs
for proper operation. Do not terminate these outputs to
ground.
The synchronization LVDS inputs (SYNC+, SYNC-) are
internally terminated with 100Ω of differential input
resistance, and therefore do not require external termi-
nation.
PECL Inputs
The serial data and clock PECL inputs (SD+, SD-,
SCLK+, SCLK-) require 50Ω termination to (VCC - 2V)
when interfacing with a PECL source (see the
Alternative PECL Input Termination section).
__________Applications Information
Alternative PECL Input Termination
Figure 4 shows alternative PECL input-termination
methods. Use Thevenin-equivalent termination when a
(VCC - 2V) termination voltage is not available. If AC
coupling is necessary, such as when interfacing with
an ECL-output device, use the ECL AC-coupling termi-
nation.
Layout Techniques
For best performance, use good high-frequency layout
techniques. Filter voltage supplies and keep ground
connections short. Use multiple vias where possible.
Also, use controlled impedance transmission lines to
interface with the MAX3681 data inputs and outputs.
THEVENIN-EQUIVALENT TERMINATION
+3.3V
130Ω
ZO = 50Ω
130Ω
MAX3681
ZO = 50Ω
PECL
INPUTS
82Ω
82Ω
+3.3V
ZO = 50Ω
ECL AC-COUPLING TERMINATION
1.6k
1.6k
MAX3681
50Ω
ZO = 50Ω -2V
PECL
INPUTS
50Ω
2.7k
2.7k
-2V
Figure 4. Alternative PECL Input Termination
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