MAX3690(1999) 查看數據表（PDF） - Maxim Integrated

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MAX3690
(Rev.:1999)

+3.3V, 622Mbps, SDH/SONET 8:1 Serializer with Clock Synthesis and TTL Inputs

Maxim Integrated 

+3.3V, 622Mbps, SDH/SONET 8:1 Serializer

with Clock Synthesis and TTL Inputs

__________Applications Information

Alternative PECL-Output Termination

Figure 3 shows alternative PECL-output-termination

methods. Use Thevenin-equivalent termination when a

(VCC - 2V) termination voltage is not available. If AC

coupling is necessary, be sure that the coupling

capacitor is placed following the 50Ω or Thevenin-

equivalent DC termination.

Layout Techniques

For best performance, use good high-frequency layout

techniques. Filter voltage supplies and keep ground

connections short. Use multiple vias where possible.

Also, use controlled-impedance transmission lines to

interface with the MAX3690 data outputs.

MAX3690

SD+

SD-

+3.3V

130Ω

130Ω

Z0 = 50Ω

Z0 = 50Ω

82Ω

PECL

INPUTS

82Ω

MAX3690

SD+

Z0 = 50Ω

SD-

Z0 = 50Ω

HIGH-

IMPEDENCE

INPUTS

50Ω

50Ω

VCC - 2V

Figure 3. Alternative PECL-Output Termination

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