MAX3881 查看數據表（PDF） - Maxim Integrated

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MAX3881

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

although the jitter tolerance performance will be

degraded. For interfacing with PECL signal levels, see

Applications Information.

Phase Detector

The phase detector in the MAX3881 produces a volt-

age proportional to the phase difference between the

incoming data and the internal clock. Because of its

feedback nature, the PLL drives the error voltage to

zero, aligning the recovered clock to the center of the

incoming data eye for retiming. The external phase

adjust pins (PHADJ+, PHADJ-) allow the user to vary

the internal phase alignment.

Frequency Detector

The digital frequency detector (FD) aids frequency

acquisition during start-up conditions. The frequency

difference between the received data and the VCO

clock is derived by sampling the in-phase and quadra-

ture VCO outputs on both edges of the data input sig-

nal. Depending on the polarity of the frequency

difference, the FD drives the VCO until the frequency

difference is reduced to zero. Once frequency acquisi-

tion is complete, the FD returns to a neutral state. False

locking is completely eliminated by this digital frequen-

cy detector.

Loop Filter and VCO

The phase detector and frequency detector outputs are

summed into the loop filter. A 1.0µF capacitor, CF, is

required to set the PLL damping ratio.

The loop filter output controls the on-chip LC VCO run-

ning at 2.488GHz. The VCO provides low phase noise

and is trimmed to the correct frequency.

Loss-of-Lock Monitor

A loss-of-lock (LOL) monitor is included in the

MAX3881 frequency detector. A loss-of-lock condition

is signaled with a TTL low. When the PLL is frequency-

locked, LOL switches to TTL high in approximately

800ns.

Note that the LOL monitor is only valid when a data

stream is present on the inputs to the MAX3881. As a

result, LOL does not detect a loss-of-power condition

resulting from a loss of the incoming signal.

Positive Emitter-Coupled

Logic (PECL) Outputs

The MAX3881 features PECL outputs for the parallel

clock and data outputs. For proper operation, PECL

outputs should be terminated with 50Ω to (VCC - 2V). In

many cases, it is not feasible to use the 50Ω to (VCC -

2V) termination, so it may be preferable to terminate to

the Thèvenin equivalent. See application note HFAN-1,

Interfacing Between CML, PECL, and LVDS for more

details regarding the Thèvenin-equivalent PECL termi-

nation.

Design Procedure

Jitter Tolerance and Input

Sensitivity Trade-Offs

When the received data amplitude is higher than

50mVp-p, the MAX3881 provides a typical jitter toler-

ance of 0.46UIp-p at jitter frequencies greater than

10MHz. The SDH/SONET jitter tolerance specification is

0.15UIp-p, leaving a jitter allowance of 0.31UIp-p for

receiver preamplifier and postamplifier design.

The BER is better than 1 x 10-10 for input signals

greater than 9.5mVp-p. At 25mVp-p, jitter tolerance will

be degraded, but will still be above the SDH/SONET

requirement. Trade-offs can be made between jitter tol-

erance and input voltage according to the specific

application. See the Typical Operating Characteristics

for Jitter Tolerance and BER vs. Input Voltage graphs.

Applications Information

Consecutive Identical Digits (CIDs)

The MAX3881 has a low phase and frequency drift in

the absence of data transitions. As a result, long runs of

consecutive zeros and ones can be tolerated while

maintaining a BER of 1 x 10-10. The CID tolerance is

tested using a 213 - 1 pseudorandom bit stream

(PRBS), substituting a long run of zeros to simulate the

worst case. A CID tolerance of greater than 2,000 bits

is typical.

Phase Adjust

The internal clock is aligned to the center of the data

eye. For specific applications, this sampling position

can be shifted using the PHADJ inputs to optimize BER

performance. The PHADJ inputs operate with differen-

tial input voltages up to ±1.5V. A simple resistor-divider

with a bypass capacitor is sufficient to set these levels

(Figure 4). When the PHADJ inputs are not used, they

should be tied directly to VCC.

System Loopback

The MAX3881 is designed to allow system loopback

testing. The user can connect a serializer output

(MAX3891) in a transceiver directly to the SLBI+ and

SLBI- inputs of the MAX3881 for system diagnostics. To

select the SLBI± inputs, apply a TTL logic high to the

SIS pin.

Interfacing with PECL Input Levels

When interfacing with differential PECL input levels, it is

important to attenuate the signal while still maintaining

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