MAX3881 查看數據表（PDF） - Maxim Integrated

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MAX3881

+3.3V, 2.488Gbps, SDH/SONET 1:16 Deserializer with Clock Recovery

Maxim Integrated 

+3.3V, 2.488Gbps, SDH/SONET

1:16 Deserializer with Clock Recovery

Typical Application Circuit

+3.3V

0.01µF

PHADJ+ PHADJ-

VCC

+3.3V

124Ω

PD15

84.5Ω

+3.3V

+3.3V

VCC

FIL

OUT+

IN+ MAX3866

PRE/POSTAMPLIFIER

OUT-

LOP

SDI+

SDI-

SLBI-

MAX3881

124Ω

PD0

84.5Ω

+3.3V

PCLK+

124Ω

84.5Ω

TTL

SLBI+

+3.3V

124Ω

SIS FIL+

FIL-

GND

SYSTEM

LOOPBACK

TTL

CF

1.0µF

LOL PCLK-

TTL

EXTERNAL TERMINATION REQUIRED ONLY IF OVERHEAD CIRCUIT DOES NOT INCLUDE INTERNAL INPUT TERMINATION.

THIS SYMBOL REPRESENTS A TRANSMISSION LINE OF CHARACTERISTIC IMPEDANCE Z0 = 50Ω.

84.5Ω

VCC

OVERHEAD

TERMINATION

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