MAX4717(2002) 查看數據表（PDF） - Maxim Integrated

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MAX4717
(Rev.:2002)

4.5Ω/20Ω, 300MHz Bandwidth, Dual SPDT Analog Switches in UCSP

Maxim Integrated 

4.5Ω/20Ω, 300MHz Bandwidth, Dual SPDT

Analog Switches in UCSP

Test Circuits/Timing Diagrams

MAX4717/

MAX4718

VN_

NO_

OR NC_

LOGIC

INPUT

IN_

GND

V+

V+

COM_

RL

VOUT

CL

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

( ) VOUT = VN_

RL

RL + RON

Figure 1. Switching Time

LOGIC VIH

INPUT VIL

50%

tr < 5ns

tf < 5ns

SWITCH 0V

OUTPUT

tOFF

VOUT 0.9 x V0UT

0.9 x VOUT

tON

IN DEPENDS ON SWITCH CONFIGURATION;

INPUT POLARITY DETERMINED BY SENSE OF SWITCH.

MAX4717/

MAX4718

VN_

LOGIC

INPUT

V+

V+

NC_

COM_

NO_

IN_

GND

VOUT

RL

300Ω

CL

35pF

CL INCLUDES FIXTURE AND STRAY CAPACITANCE.

Figure 2. Break-Before-Make Interval

LOGIC VIH

INPUT

50%

VIL

VOUT

0.9 x VOUT

tBBM

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